Antifuse-type one time programming memory and associated bias voltage control method

An antifuse-type one time programming memory comprising a first memory cell, the first memory cell comprising:

• a P-type semiconductor substrate;
• a P-type well region formed in a surface of the P-type semiconductor substrate;
• an N-type region formed in the P-type semiconductor substrate and located under the P-type well region, wherein a region of the P-type semiconductor substrate underlying the N-type region and the P-type well region are separated from each other through the N-type region, and the P-type well region is formed as an isolated P-type well region;
• a first nanowire;
• a first gate structure comprising a first spacer, a second spacer, a first gate dielectric layer and a first gate layer, wherein the first gate dielectric layer surrounds a central region of the first nanowire, the first gate layer covers the first gate dielectric layer, the first gate layer is electrically connected with a first word line, a first terminal of the first nanowire is surrounded by the first spacer, a second terminal of the first nanowire is surrounded by the second spacer, and the first spacer and the second spacer are located over the P-type well region;
• a first drain/source structure located over the P-type well region and electrically contacted with the first terminal of the first nanowire, wherein the first drain/source structure is electrically connected with a first bit line;
• a second drain/source structure located over the P-type well region and electrically contacted with the second terminal of the first nanowire, wherein the first nanowire, the first gate structure, the first drain/source structure and the second drain/source structure are collaboratively formed as a first select transistor;
• a second nanowire;
• a second gate structure comprising a third spacer, a fourth spacer, a second gate dielectric layer and a second gate layer, wherein the second gate dielectric layer surrounds a central region of the second nanowire, the second gate layer covers the second gate dielectric layer, the second gate layer is electrically connected with a first antifuse control line, the first terminal of the second nanowire is surrounded by the third spacer, a second terminal of the second nanowire is surrounded by the fourth spacer, and the third spacer and the fourth spacer are located over the P-type well region;
• a third drain/source structure located over the P-type well region and electrically contacted with the first terminal of the second nanowire, wherein the third drain/source structure is coupled to the second drain/source structure;
• a fourth drain/source structure located over the P-type well region and electrically contacted with the second terminal of the second nanowire, wherein the second nanowire, the second gate structure, the third drain/source structure and the fourth drain/source structure are collaboratively formed as a first antifuse transistor;
• wherein when a program action is performed, the P-type well region receives a negative program voltage, the N-type region receives a first voltage, and the P-type semiconductor substrate receives a second voltage, a region between the P-type well region and the N-type region is in a reverse bias condition, and a region between the P-type semiconductor substrate and the N-type region is in the reverse bias condition or a zero bias condition,
• wherein the first voltage is higher than or equal to a ground voltage, the second voltage is higher than or equal to the negative program voltage, and the second voltage is lower than or equal to the first voltage.