US 2025/0063722 A1Published application

Memory Devices and Methods of Forming Memory Devices

AssigneeMicron Technology, Inc.

InventorsGiorgio Servalli, Marcello Mariani

Life of this patent

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Abstract

Some embodiments include an assembly having first and second pillars. Each of the pillars has an inner edge and an outer edge. A first gate is proximate a channel region of the first pillar. A second gate is proximate a channel region of the second pillar. A shield line is between the first and second pillars. First and second bottom electrodes are over the first and second pillars, respectively; and are configured as first and second angle plates. An insulative material is over the first and second bottom electrodes. The insulative material may be ferroelectric or non-ferroelectric. A top electrode is over the insulative material. Some embodiments include methods of forming assemblies.

Claims14

Dependent claims

A method of forming an integrated assembly, comprising:

forming a construction having first and second pillars of semiconductor material, the first and second pillars having first and second source/drain regions, respectively;
forming a first bottom-electrode-structure over the first source/drain region and a second bottom-electrode-structure over the second source/drain region;
the first bottom-electrode-structure having a first vertical segment and a first horizontal segment along the first source/drain region, and a first corner joining the first vertical segment to the first horizontal segment;
the second bottom-electrode-structure having a second vertical segment and a second horizontal segment along the second source/drain region, and a second corner joining the second vertical segment to the second horizontal segment;
forming an insulative material over the first and second bottom-electrode-structures;
and
forming a top-electrode-material over the insulative material.

4 more elements

Dependencies are inferred from the claim text.

Facts

Application: 18/935,844Filed 4 Nov 2024
Priority: 8 Jan 2020
Published: 20 Feb 2025
Term ends: Not estimatedThe source records don’t support an estimate.

Classification11 codes

H10B 12/315
Having a storage electrode stacked over the transistor: with the capacitor higher than a bit line
G11C 11/221
Using ferroelectric elements: using ferroelectric capacitors
H10B 12/0335
The capacitor extending over the transistor: making a connection between the transistor and the capacitor, e.g. plug
H10B 12/05
For one transistor one-capacitor [1T-1C] memory cells: making the transistor

Family

Application16/737,171Continuation · filed 8 Jan 2020
Application17/460,156Division · filed 27 Aug 2021
Application18/935,844Division
Application17/460,156Continuation
US 11,127,744 B2Related patent
US 12,167,586 B2Related patent
US 2021/0210491 A1Published application
US 2021/0391334 A1Published application
US 2025/0063722 A1This patent

From the US filing history. Foreign family members aren’t listed.

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