Semiconductor device and manufacturing method thereof

A semiconductor device, comprising:

• a substrate, having a logic region comprising a plurality of first transistors and a peripheral region comprising a plurality of second transistors and next to the logic region;
• a back-end-of-line (BEOL) routing structure, disposed over the substrate and interconnecting the plurality of first transistors and the plurality of second transistors;
• a plurality of selectors, disposed in the BEOL routing structure within the peripheral region;
• a plurality of storage capacitors, disposed over and electrically coupled to the plurality of selectors, respectively;
• and
• a plurality of barrier structures, lining a sidewall and a bottom surface of at least one conductive element of the plurality of storage capacitor or the plurality of selectors, and each comprising:
• a first barrier layer;
• and
• a second barrier layer, disposed between the at least one conductive element and the first barrier layer, wherein a first absorption interface is disposed between the first barrier layer and the second barrier layer.

A method of manufacturing a semiconductor device, comprising:

• providing a substrate;
• forming a plurality of build-up layers over the substrate;
• disposing a memory cell over a portion of the plurality of build-up layers within a memory region of the substrate, the memory cell comprising a transistor and a capacitor disposed over the transistor, the transistor comprising a gate, source/drain elements respectively standing at two opposite sides of the gate, and a channel disposed between the source/drain elements and overlapped with the gate, and the capacitor being electrically coupled to one of the source/drain elements;
• forming a plurality of barrier structures lining sidewalls and bottom surfaces of the source/drain elements, the plurality of barrier structures each comprising a first barrier layer and a second barrier layer disposed between the source/drain elements and the first barrier layer, wherein a first absorption interface is formed between one first barrier layer and a respective one second barrier layer;
• and
• forming a topmost build-up layer over the memory cell to form an interconnect of the substrate.