Memory devices including capacitors

A memory device, comprising:

• an array region comprising:
• volatile memory cells;
• and
• control logic circuitry vertically overlying the volatile memory cells and comprising sense amplifier devices and sub-word line driver devices coupled to the volatile memory cells;
• and
• a capacitor region horizontally neighboring the array region and comprising:
• capacitors vertically overlapping the volatile memory cells within the array region;
• and
• additional circuitry vertically overlying the capacitors and comprising charge pump devices coupled to the capacitors.

A memory device, comprising:

• a memory array structure comprising:
• an array of dynamic random access memory (DRAM) cells, the DRAM cells respectively comprising a capacitor vertically underlying and coupled to an access device;
• and
• an array of additional capacitors horizontally offset from the array of DRAM cells;
• a control circuitry structure vertically overlying and attached to the memory array structure through dielectric-to-dielectric bonds, the control circuitry structure comprising:
• sense amplifier circuitry coupled to digit lines coupled to the array of DRAM cells;
• sub-word line driver circuitry coupled to word lines coupled to the array of DRAM cells;
• and
• additional circuitry coupled to a capacitor cell plate coupled to the array of additional capacitors.