Storage node contact (snc) junction formation for three-dimensional dynamic random access memory (dram)

A method for semiconductor processing, comprising:

• providing a stacked semiconductor structure, the stacked semiconductor structure comprising a plurality of unit stacks formed on a substrate, each unit stack comprising a semiconductor layer having a first lateral end and a second lateral end, a first dielectric layer formed on the semiconductor layer, a first gate electrode formed on the first dielectric layer, and a second dielectric layer of a capacitor portion, wherein a lateral recess that is bounded by the second dielectric layer at a top and a bottom and by the second lateral end of the semiconductor layer at a first side, and the lateral recess open to a first opening through the unit stack of the stacked semiconductor structure at a second side;
• conformally depositing, in the lateral recess, a doped silicon layer on the second lateral end of the semiconductor layer;
• performing a thermal annealing process after forming the doped silicon layer on the second lateral end;
• and
• forming a capacitor where the lateral recess was disposed, the capacitor contacting the doped silicon layer on the second lateral end of the semiconductor layer.

A method for semiconductor processing, comprising:

• forming a stacked semiconductor structure comprising a plurality of unit stacks formed on a substrate, each unit stack comprising a semiconductor layer, a first dielectric layer formed on the semiconductor layer, and a second dielectric layer of a capacitor portion of the stacked semiconductor structure, the semiconductor layer having a first lateral end and a second lateral end opposite the first lateral end;
• forming a first opening through the unit stack;
• forming a lateral recess from the first opening to expose the second lateral end of the semiconductor layer;
• conformally depositing a doped silicon layer in the lateral recess, including a vertical portion on the second lateral end and lateral portions coupled with the vertical portion;
• forming a third dielectric layer on the doped silicon layer in the lateral recess;
• pulling back the third dielectric layer to expose the vertical portion of the doped silicon layer;
• removing the third dielectric layer as a sacrificial layer;
• pulling back the vertical portion and the lateral portions of the doped silicon layer;
• and
• performing a thermal annealing process after conformally depositing the doped silicon layer, after third dielectric layer deposition, or after pulling back the doped silicon layer, or after full removal of the third dielectric layer.