Clock data recovery circuit and apparatus including the same

A clock data recovery circuit comprising:

• an inphase-quadrature (I-Q) merged phase interpolator circuit configured to generate a first clock pair and a second clock pair from a plurality of reference clock signals, the plurality of reference clock signals having different phases, the first clock pair comprising an I clock signal and an inverted I clock signal, and the second clock pair comprising a Q clock signal and an inverted Q clock signal;
• a sampler circuit configured to sample input data based on the first clock pair and the second clock pair;
• and
• a control circuit configured to control phases of the first clock pair and the second clock pair, the controlling including providing a control signal to the I-Q merged phase interpolator circuit based on a sampling result of the sampler circuit,
• wherein the I-Q merged phase interpolator includes:
• a decoder configured to generate a phase interpolation code from the control signal,
• a plurality of digital to analog converting (DAC) circuits configured to generate a plurality of analog inputs based on the phase interpolation code and coupled in parallel with each other to share a plurality of output nodes outputting the plurality of analog inputs, and
• a plurality of phase mixers configured to commonly receive the plurality of analog inputs from the plurality of output nodes and to generate the first clock pair and the second clock pair based on the plurality of analog inputs.

An apparatus comprising:

• a receiving circuit;
• and
• a transmitting circuit configured to transmit input data to the receiving circuit through a channel,
• wherein the receiving circuit comprises a clock data recovery circuit including,
• an inphase-quadrature (I-Q) merged phase interpolator circuit configured to generate analog inputs based on a phase interpolation code and receive the analog inputs to generate an I clock signal, an inverted I clock signal, a Q clock signal, and an inverted Q clock signal,
• a sampler circuit configured to sample input data based on the I clock signal, the inverted I clock signal, the Q clock signal, and the inverted Q clock signal, and
• a control circuit configured to control phases of the the I clock signal, the inverted I clock signal, the Q clock signal based on a sampling result of the sampler circuit.