Puf memory devices and methods of manufacturing thereof
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsMeng-Sheng Chang, Yih Wang
Life of this patent
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Abstract
A memory device includes an array comprising a plurality of one-time-programmable (OTP) memory cells; a plurality of word lines (WLs); a plurality of bit lines (BLs); and a plurality of control gate (CG) lines. Each of the OTP memory cells comprises a first fuse resistor, a second fuse resistor, a first transistor, and a second transistor. The first fuse resistor and the second fuse resistor are coupled to a corresponding one of the BLs, while the first transistor and the second transistor are gated by a first one and a second one of the CG lines, respectively.
Claims20
A memory device, comprising:
- an array comprising a plurality of one-time-programmable (OTP) memory cells;
- a plurality of word lines (WLs);
- a plurality of bit lines (BLs);
- and
- a plurality of control gate (CG) lines;
- wherein each of the OTP memory cells comprises a first fuse resistor, a second fuse resistor, a first transistor, and a second transistor;
- and
- wherein the first fuse resistor and the second fuse resistor are coupled to a corresponding one of the BLs, while the first transistor and the second transistor are gated by a first one and a second one of the CG lines, respectively.
A memory device, comprising:
- a memory cell that comprises:
- a first fuse resistor;
- a second fuse resistor;
- a first transistor connected to the first fuse resistor in series;
- and
- a second transistor connected to the second fuse resistor in series;
- wherein the memory cell is configured to randomly present a first logic state when the first fuse resistor is blown, or a second logic state when the second fuse resistor is blown.
A method for forming a memory device, comprising:
- forming at least, a first transistor, a second transistor, and a third transistor on a first side of a substrate;
- forming a first fuse resistor and a second fuse resistor in one of a plurality of first metallization layers that are disposed over the first to third transistors on the first side;
- and
- forming a power rail in one of a plurality of second metallization layers that are disposed on a second side of the substrate opposite to the first side.
Dependencies are inferred from the claim text.