Semiconductor package and integrated circuit device

A semiconductor package comprising:

• a package substrate;
• a first semiconductor chip on the package substrate, and includes a first power bump on a first lower face that faces the package substrate;
• a second semiconductor chip which is spaced apart from the first semiconductor chip on the package substrate, and includes a second power bump on a second lower face that faces the package substrate;
• and
• a bridge die below the first semiconductor chip and the second semiconductor chip on the package substrate, and connects the first semiconductor chip and the second semiconductor chip,
• wherein the bridge die includes,
• a connection wiring structure on a first face that faces the first semiconductor chip and the second semiconductor chip, and connects the first semiconductor chip and the second semiconductor chip,
• a power wiring structure on a second face that faces the package substrate, and is spaced apart from the connection wiring structure, and
• a substrate between the connection wiring structure and the power wiring structure,
• wherein the package substrate includes a power ball on a lower face of the package substrate and connected to the power wiring structure, and
• the power wiring structure is connected to the first power bump and the second power bump.

An integrated circuit device comprising:

• a package substrate;
• a first semiconductor chip on the package substrate;
• a second semiconductor chip spaced apart from the first semiconductor chip on the package substrate;
• and
• a bridge die on the package substrate and between the first semiconductor chip and the second semiconductor chip,
• wherein the bridge die includes,
• a first face that faces the first semiconductor chip and the second semiconductor chip,
• a second face that faces the package substrate,
• a connection wiring structure on the first face, and connects the first semiconductor chip and the second semiconductor chip, and
• a power wiring structure on the second face, and is configured to supply power to the first semiconductor chip and the second semiconductor chip,
• wherein a level of signal provided to the connection wiring structure is smaller than a level of signal provided to the power wiring structure.