US 2025/0062223 A1 · SEMICONDUCTOR STRUCTURE

Abstract

A semiconductor structure includes a first cell, a second cell, a first bit line, a first source line, a second bit line, and a second source line. The first cell includes a first source structure and a first drain structure. The second cell includes a second source structure and a second drain structure. The first bit line is coupled to the first drain structure, the first source line is coupled to the first source structure, the second bit line is coupled to the second drain structure, and the second source line is coupled to the second source structure. The first source line and the first bit line are alternately arranged, and the second source line and the second bit line are alternately arranged. A distance between the first source line and the first bit line is similar to a distance between the second source line and the second bit line.

Claims20

Dependent claims

A semiconductor structure comprising:

a first cell comprising a first source structure and a first drain structure;
a second cell comprising a second source structure and a second drain structure;
a first bit line coupled to the first drain structure and a first source line coupled to the first source structure;
and
a second bit line coupled to the second drain structure and the second source line coupled to a second source structure,
wherein the first source line and the first bit line are alternately arranged, and the second source line and the second bit line are alternately arranged, and
wherein a distance between the first source line and the first bit line is similar to a distance between the second source line and the second bit line.

4 more elements

A semiconductor structure comprising:

a first conductive line electrically connected to a first drain structure of a first cell and a second conductive line electrically connected to a first source structure of the first cell;
a third conductive line electrically connected to a second drain structure of a second cell and a fourth conductive line electrically connected to a second source structure of the second cell;
a first bit line electrically connected to the first drain structure through the first conductive line;
a first source line electrically connected to the first source structure through the second conductive line;
a second bit line electrically connected to the second drain structure through the third conductive line;
and
a second source line electrically connected to the second source structure through the fourth conductive line;
wherein the first conductive line, the second conductive line, the third conductive line and the fourth conductive line are disposed in a first common layer, and
wherein the second source line and the second bit line are disposed in a second common layer over the first common layer.

6 more elements

A semiconductor structure comprising:

a first source structure and a first drain structure of a first cell, and a second source structure and a second drain structure of a second cell, wherein the first source structure, the first drain structure, the second source structure and the second drain structure are disposed in a first common layer and extend in a first direction;
a first conductive line electrically connected to the first source structure, a second conductive line electrically connected to the first drain structure, a third conductive line electrically connected to the second source structure, and a fourth conductive line electrically connected to the second drain structure, wherein the first conductive line, the second conductive line, the third conductive line and the fourth conductive line are disposed in a second common layer and extend in the first direction;
and
a first source line electrically connected to the first conductive line, a first bit line electrically connected to the second conductive line, a second source line electrically connected to the third conductive line and a second bit line electrically connected to the fourth conductive line, wherein the first source line, the first bit line, the second source line, and the second bit line extend in a second direction different from the first direction.

1 more element

Dependencies are inferred from the claim text.

Facts

Application

18/934,261Filed 1 Nov 2024

Priority

5 Jan 2021

Published

20 Feb 2025

Term ends

Not estimatedThe source records don’t support an estimate.

Classification7 codes

H10B 43/10
EEPROM devices comprising charge-trapping gate insulators: characterised by the top-view layout
H10W 20/42
Characterised by their conductive parts: vias, e.g. via plugs
H10B 43/27
With source and drain on different levels, e.g. with sloping channels: the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/50
EEPROM devices comprising charge-trapping gate insulators: characterised by the boundary region between the core and peripheral circuit regions

Family

Application17/142,158Division · filed 5 Jan 2021

Application18/492,811Continuation · filed 24 Oct 2023

Application18/934,261Continuation

Application18/492,811Division

US 11,837,536 B2Related patent

US 12,165,970 B2Related patent

US 2022/0216142 A1Published application

US 2024/0055349 A1Published application

US 2025/0062223 A1This patent

From the US filing history. Foreign family members aren’t listed.

Semiconductor structure

Life of this patent

Semiconductor structure

Life of this patent

Abstract

Claims20