Package structure and method for forming same

A method for forming a package structure, comprising:

• providing a substrate, wherein the substrate comprises a first surface and a second surface that are opposite, a plurality of first connection terminals being arranged on the first surface of the substrate, a plurality of second connection terminals being arranged on the second surface of the substrate, the plurality of first connection terminals being correspondingly electrically connected to the plurality of second connection terminals;
• mounting passive devices on the first surface of the substrate, wherein the passive devices are correspondingly electrically to the plurality of first connection terminals on the first surface of the substrate;
• forming a first molding layer encapsulating the passive devices and covering the first surface of the substrate;
• providing a first chip comprising a back face and a functional face that are opposite, wherein a plurality of external terminals are arranged on the functional face;
• mounting the back face of the first chip on the second surface of the substrate;
• providing metal connection structures, wherein each of the metal connection structures comprises a horizontal metal strip and a vertical metal pin electrically connected to the horizontal metal strip, the vertical metal pin protruding from a bottom surface of the horizontal metal strip;
• mounting the metal connection structures on the second surface of the substrate, the vertical metal pins of the metal connection structures are correspondingly electrically connected to the plurality of second connection terminals on the second surface of the substrate, and the horizontal metal strips of the metal connection structures are correspondingly electrically connected to a portion of the plurality of external terminals on the functional face of the first chip;
• forming a second molding layer encapsulating the metal connection structures and the first chip and covering the second surface of the substrate, wherein the second molding layer exposes top surfaces of another portion of the plurality of external terminals on the functional face of the first chip;
• and
• forming first solder bumps on the exposed top surfaces of the plurality of external terminals.