Semiconductor package and method of manufacturing the same

A semiconductor package comprising:

• a lower redistribution layer;
• a semiconductor chip on an upper surface of the lower redistribution layer, the semiconductor chip having an area that is less than an area of the lower redistribution layer;
• a conductive post on the upper surface of the lower redistribution layer and spaced apart from the semiconductor chip in a horizontal direction;
• a plate group on the upper surface of the lower redistribution layer, the plate group comprising a plurality of conductive plates facing each other and extending in a same direction;
• a molding layer covering the upper surface of the lower redistribution layer and surrounding the semiconductor chip, the conductive post, and the plate group;
• and
• an upper redistribution layer on the molding layer and the conductive post,
• wherein the plurality of conductive plates extend along a plane on the upper surface of the lower redistribution layer in a first horizontal direction and a second horizontal direction perpendicular to the first horizontal direction, and each of the plurality of conductive plates has a length in the first horizontal direction that is greater than a length in the second horizontal direction.

A semiconductor package comprising:

• a lower redistribution layer;
• a semiconductor chip on an upper surface of the lower redistribution layer, the semiconductor chip having an area that is less than an area of the lower redistribution layer;
• a conductive post on the upper surface of the lower redistribution layer and space apart from the semiconductor chip in a horizontal direction, the conductive post having a cylindrical shape;
• a first plate group comprising a plurality of first conductive plates on the upper surface of the lower redistribution layer and between the conductive post and the semiconductor chip, the plurality of first conductive plates facing each other and extending in a first same direction;
• a second plate group comprising a plurality of second conductive plates on the upper surface of the lower redistribution layer and between the conductive post and the semiconductor chip, facing each other, the plurality of second conductive plates extending in a second same direction;
• a molding layer covering the upper surface of the lower redistribution layer and surrounding the semiconductor chip, the conductive post, the first plate group, and the second plate group;
• and
• an upper redistribution layer on the molding layer and the conductive post,
• wherein each of the plurality of first conductive plates extends along a plane on the lower redistribution layer in a first horizontal direction and a second horizontal direction perpendicular to the first horizontal direction, and the first horizontal direction of the plurality of first conductive plates is different from the first horizontal direction of the plurality of second conductive plates,
• wherein a length of a diameter of the conductive post is less than a length of each of the plurality of first conductive plates in the first horizontal direction and greater than a length each of the plurality of first conductive plates in the second horizontal direction, and
• wherein the length of the diameter of the conductive post is less than a length of each of the plurality of second conductive plates in the first horizontal direction and greater than a length of each of the plurality of second conductive plates in the second horizontal direction.