Semiconductor package comprising dummy structure at corner region thereof

A semiconductor package comprising:

• a first semiconductor die;
• a second semiconductor die on the first semiconductor die;
• a mold layer that overlaps the second semiconductor die and the first semiconductor die;
• external connection terminals on the first semiconductor die;
• internal connection members between the first semiconductor die and the second semiconductor die;
• and
• an underfill layer in a space between the first semiconductor die and the second semiconductor die,
• wherein the first semiconductor die comprises:
• a first substrate comprising a main region and first corner regions, wherein the first corner regions overlap the second semiconductor die, wherein the first corner regions are adjacent to respective corners of the second semiconductor die, and wherein the main region overlaps a center of the second semiconductor die in a first direction;
• through vias that extend into the main region of the first substrate;
• redistribution patterns that are on the first substrate and comprise dummy wirings and signal wirings;
• a redistribution insulating layer on the redistribution patterns;
• and
• conductive pads that are on the redistribution insulating layer and comprise dummy pads and signal pads,
• wherein a distance between a first set of the conductive pads on the first corner regions is less than a distance between a second set of the conductive pads on the main region,
• wherein the second semiconductor die comprises:
• a second substrate;
• an interlayer insulating layer on a lower surface of the second substrate;
• internal wirings in the interlayer insulating layer;
• and
• conductive bumps on the interlayer insulating layer, and
• wherein the internal connection members electrically connect at least some of the conductive bumps to ones of the signal pads.

A semiconductor package comprising:

• a first semiconductor die;
• a second semiconductor die on the first semiconductor die;
• and
• an underfill layer between the first semiconductor die and the second semiconductor die,
• wherein the first semiconductor die comprises:
• a substrate comprising a main region and first corner regions, wherein the first corner regions overlap the second semiconductor die, wherein the first corner regions are adjacent to respective corners of the second semiconductor die, and wherein the main region overlaps a center of the second semiconductor die in a first direction;
• signal wirings and dummy wirings on the substrate;
• a redistribution insulating layer that is on the signal wirings and the dummy wirings;
• and
• conductive pads on the redistribution insulating layer,
• wherein the conductive pads comprise signal pads and dummy pads, and
• wherein a first one of the dummy wirings electrically connects a first one of the dummy pads and a first one of the signal pads.