Semiconductor package

A semiconductor package, comprising:

• a package substrate having a plurality of upper connection pads on a top surface thereof;
• a first semiconductor device on the package substrate and electrically connected to a first subset of the plurality of upper connection pads;
• and
• a package encapsulant including a first encapsulant and a second encapsulant, wherein the first encapsulant is on the package substrate and is in contact with at least some side surfaces of the first semiconductor device at a perimeter of the first semiconductor device, and the second encapsulant is on the package substrate and laterally spaced from a second subset of the plurality of upper connection pads, and at least partially encloses the second subset of the plurality of upper connection pads, wherein
• the first encapsulant and the second encapsulant are integrally provided, and
• a first height, which is a vertical level of the first encapsulant relative to the top surface of the package substrate, is greater than a second height, which is a vertical level of the second encapsulant relative to the top surface of the package substrate,
• the first height is equal to or greater than a third height, which is a vertical level of a top surface of the first semiconductor device relative to the top surface of the package substrate, and
• some side surfaces of the package encapsulant are coplanar with an outer edge of the package substrate.

A semiconductor package, comprising:

• a package substrate having a plurality of upper connection pads on a top surface thereof;
• a first semiconductor device on the package substrate and electrically connected to a first subset of the plurality of upper connection pads;
• and
• a package encapsulant including a first encapsulant and a second encapsulant, wherein the first encapsulant is on the package substrate and in contact with at least some side surfaces of the first semiconductor device at a perimeter of the first semiconductor device, and the second encapsulant is on the package substrate and laterally spaced from a second subset of the plurality of upper connection pads, and at least partially encloses the second subset of the plurality of upper connection pads, wherein
• the first encapsulant and the second encapsulant are integrally provided, and
• a first height, which is a vertical level of the first encapsulant relative to the top surface of the package substrate, is greater than a second height, which is a vertical level of the second encapsulant relative to the top surface of the package substrate, the second height is less than or equal to half the first height,
• the first height is equal to or greater than a third height, which is a vertical level of a top surface of the first semiconductor device relative to the top surface of the package substrate, and
• some side surfaces of the package encapsulant are coplanar with an outer edge of the package substrate.