Logic device and system and methods for definition and configuration of a logic device
OwnerClément AYMEinventor
Life of this patent
Estimating the term…
Loading patent…
OwnerClément AYMEinventor
Estimating the term…
A method of defining a logic device is provided wherein the definition incorporates the definition of special auxiliary memory cells reserved for the presentation of a special code, incorporating a signature of the definition as a whole so as to constitute a watermark securing the design as a whole, and possibly other information. In certain embodiments, the special code may incorporate recursive signatures from preceding versions of the same device to as to constitute a watermark blockchain. A LUT based FPGA architecture is proposed with special addressable memory cells reserved for this purpose, wherein case a programming bitstream may constitute a definition in accordance with the inventive method.
A computer implemented method of defining a device capable of implementing a logic function, said device comprising a memory bus having a corresponding address space, and a plurality of programme memory cells, each said programme memory cell being accessible for reading and/or writing via said memory bus with a respective address in said address space, wherein said device further comprises a plurality of auxiliary memory cells, each said auxiliary memory cell being accessible for reading via said programme memory bus with a respective address in said address space, said select lines and/or outputs of each lookup table being programmably interconnected with the select lines or outputs of another said lookup table independently of the respective values of said plurality of auxiliary memories, said method comprising
A Field Programmable Gate Array capable of implementing a logic function, said Field Programmable Gate Array comprising a plurality of hardware lookup tables each comprising a plurality of select lines and/or outputs, a programme memory bus having a corresponding address space, and a plurality of programme memory cells, each said programme memory cell being accessible for reading and/or writing via said programme memory bus with a respective address in said address space, the select lines and/or outputs of each lookup table being programmably interconnected with the select lines or outputs of another said lookup table dependent on the respective values of said plurality of programme memories,
Dependencies are inferred from the claim text.