Memory device and read operation during suspension of program operation thereof

A memory system, comprising:

• a memory device comprising:
• an array of memory cells comprising a first memory cell and a second memory cell, wherein each of the first memory cell and the second memory cell is configured to store N-bits data;
• and
• a peripheral circuit coupled to the array of memory cells and comprising:
• a page buffer comprising at least a page buffer circuit that is coupled to the first and second memory cells, respectively, the page buffer circuit comprising a sense out (SO) node and a cache storage unit;
• and
• control logic coupled to the page buffer and configured to:
• suspend a program operation on the first memory cell responsive to receiving a suspension command indicative of executing a read operation on the second memory cell;
• control the page buffer circuit to store suspended program information associated with a suspension of the program operation;
• and
• perform the read operation on the second memory cell, comprising directly storing one of N-bits data of the second memory cell into the cache storage unit through the SO node;
• and
• a memory controller coupled to the memory device and configured to control the memory device.

A method for operating a memory device comprising an array of memory cells, the array of memory cells comprising a first memory cell and a second memory cell that are coupled to a page buffer circuit in a page buffer, each of the first memory cell and the second memory cell configured to store N-bits data, the page buffer circuit comprising a sense out (SO) node and a cache storage unit, the method comprising:

• suspending a program operation on the first memory cell responsive to receiving a suspension command indicative of executing a read operation on the second memory cell;
• controlling the page buffer circuit to store suspended program information associated with a suspension of the program operation;
• and
• performing the read operation on the second memory cell, comprising directly storing one of N-bits data of the second memory cell into the cache storage unit through the SO node.