Memory control circuit capable of generating an updated reference current

A memory control circuit comprising:

• a leakage current providing circuit configured to generate a leakage current, and comprising a first terminal configured to receive a control signal, and a second terminal configured to provide the leakage current when the control signal has a first enable signal level;
• a current mirror circuit configured to generate a control current according to the leakage current, the current mirror circuit comprising a first terminal coupled to the second terminal of the leakage current providing circuit, and a second terminal configured to output the control current;
• an operation circuit configured to generate an enable signal, the operation circuit comprising a first terminal coupled to the second terminal of the current mirror circuit, and a second terminal configured to output the enable signal, wherein the enable signal has a second enable signal level when the control current is larger than a predetermined value;
• and
• a reference current adjustment circuit coupled to the second terminal of the operation circuit and configured to generate an updated reference current according to a reference current and an adjustment current when the enable signal has the second enable signal level;
• wherein a resistance of a memory is determined according to the updated reference current.