Memory device including sense amplifier and method of storing data thereof

A memory device comprising:

• a peripheral circuit area;
• and
• a memory cell area stacked on the peripheral circuit area,
• wherein the memory cell area comprises a memory cell array including normal memory cells and error correction code cells,
• wherein the peripheral circuit area comprises:
• a single-ended bitline sense amplifier connected to the memory cell array through a bitline and a complementary bitline, and electrically connected through one of the bitline and the complementary bitline when the memory cell array is activated;
• a DSI circuit configured to conditionally transmit complementary input data generated by inverting input data to the single-ended bitline sense amplifier in response to a first number of bits included in the input data having a first level greater than a second number of bits included in the input data having a second level, and a data inversion flag indicating that the input data is inverted, to the single-ended bitline sense amplifier;
• and
• a DSI register configured to store the data inversion flag,
• wherein the single-ended bitline sense amplifier is configured to store the complementary input data in the memory cell array and store the data inversion flag in the DSI register.

A method of storing data in a memory device including a single-ended bitline sense amplifier, the method comprising:

• receiving input data;
• determining logic levels of bits included in the input data;
• generating a data inversion flag corresponding to the input data in response to a first number of bits of the input data having a first level being greater than a second number of bits of the input data having a second level;
• inverting the input data into complementary input data;
• storing the complementary input data in a memory cell array;
• and
• storing the data inversion flag in a specified area.