Truncated Resolution for Time Sliced Computation of Multiplication and Accumulation using a Memory Cell Array

A device, comprising:

• a plurality of memory cells programmable to represent a plurality of weights;
• a plurality of wordlines connected to the plurality of memory cells;
• a bitline connected to collect currents going through the plurality of memory cells;
• voltage drivers operable to apply, to the plurality of memory cells via the plurality of wordlines, a plurality of voltages according to a bit slice having a slice weight in an input;
• an analog to digital converter coupled to the bitline and configured with a resolution control;
• and
• a logic circuit configured to apply the resolution control according to the slice weight in measurement of, using the analog to digital converter, at least one first bit of a quantity representative of a magnitude of a current in the bitline responsive to the plurality of voltages being applied to the plurality of memory cells;
• and
• wherein the logic circuit is configured to sum a plurality of truncated outputs resulting from a plurality of bit slices having a plurality of slice weights respectively in the input, the plurality of truncated outputs including a truncated output having the at least one first bit but.

A system, comprising:

• a memory cell array having a plurality of memory cells connected to a plurality of wordlines and a bitline;
• voltage drivers;
• and
• at least one analog to digital converter;
• a processor configured to:
• program the plurality of memory cells to store a plurality of weights;
• identify a bit slice having a slice weight in an input;
• instruct the voltage drivers to apply, via the wordlines, a plurality of voltages according to the bit slice;
• and
• instruct the analog to digital converter to generate a truncated output from measurement of a current in the bitline resulting from the plurality of memory cells responsive to the plurality of voltages, wherein the analog to digital converter to measure at least one first bit of a quantity representative of a magnitude of the current in the line responsive to the plurality of voltages;
• wherein the system is configured sum a plurality of truncated outputs, resulting from a plurality of bit slices having a plurality of slice weights respectively in the input, to provide an approximated result of a sum of the input having a plurality of elements weighted by the plurality of weights respectively.