Pixel group, array substrate, and display panel

An array substrate, comprising:

• a substrate;
• and
• a plurality of pixel groups, located at a side of the substrate, wherein the pixel group comprises a plurality of pixel circuits and a compensation circuit;
• each of the pixel circuits is connected to the compensation circuit;
• wherein
• each of the pixel circuits comprises a driving transistor;
• the compensation circuit comprises a third transistor;
• and the compensation circuit is capable of loading a threshold voltage of the third transistor to a control end of the driving transistor;
• and
• a channel region of the third transistor has a width to length ratio of a3, a channel region of the driving transistor has a width to length ratio of a1, and a3/a1 is in a range of 1-1.05.