Disaggregation of system-on-chip (soc) architecture

A method of assembling an accelerator device including a plurality of chiplets, the method comprising:

• assembling a package assembly including a first base chiplet comprising a first interconnect fabric and a first plurality of level 3 (L3) cache banks coupled to or integrated with the first interconnect fabric;
• stacking a first logic chiplet on the first base chiplet, the first logic chiplet comprising a cluster of compute units to perform parallel execution of compute shader instructions or graphics shader instructions;
• coupling the cluster of compute units to the first interconnect fabric via a first interconnect structure;
• and
• coupling the first base chiplet to a second base chiplet by a second interconnect structure, the second base chiplet comprising a second interconnect fabric and a second plurality of L3 cache banks coupled to or integrated with the second interconnect fabric, wherein the first logic chiplet is manufactured using a different process technology than that used to manufacture the first base chiplet and the second base chiplet.

A graphics processing system comprising:

• a first base chiplet comprising:
• a first interconnect fabric;
• and
• a first plurality of level 3 (L3) cache banks coupled to or integrated with the first interconnect fabric;
• a first logic chiplet stacked on the first base chiplet, the first logic chiplet comprising:
• a cluster of compute units for parallel execution of compute shader instructions and graphics shader instructions;
• and
• a first interconnect structure coupling the cluster of compute units to the first interconnect fabric;
• and
• a second base chiplet comprising;
• a second interconnect fabric;
• a second plurality of L3 cache banks coupled to or integrated with the second interconnect fabric;
• an interface to a second logic chiplet, wherein the interface to the second logic chiplet is configurable to couple with a plurality of different types of chiplets and includes a third interconnect structure to couple the second logic chiplet to the second interconnect fabric,
• wherein the first logic chiplet is manufactured using a different process technology than that used to manufacture the first base chiplet and the second base chiplet, and
• at least one of the first base chiplet and second base chiplet further comprise a fourth interconnect structure to couple at least one of the first base chiplet and the second base chiplet to a memory.