Automated Method for Printed Circuit Board Inter-Layer Element Clearance

Abstract

A computer-implemented method for evaluating a minimum clearance distance between a first conductive element and a second conductive element included in a printed circuit board (PCB) is provided. The PCB comprises a plurality of conductive layers and a plurality of conductive elements, where each conductive layer comprises one or more conductive elements. The plurality of conductive layers comprises one or more outer conductive layers. The method comprises selecting a first conductive element (A) disposed on a first outer conductive layer and a second conductive element (B) disposed on a second outer conductive layer of the PCB, a clearance between which has a minimum spacing requirement. The method also comprises creating polygons of the first and second conductive elements, wherein a polygon of the first conductive element is A′ and a polygon of the second conductive element is B′. The method also comprises determining if there is at least one conductive layer disposed between A′ and B′. If no conductive layer is disposed between A′ and B′, then A″ and B″ are created on an evaluation layer. The method further comprises calculating a shortest unshielded distance (dxy) between A″ and B″. The method also comprises using a distance between the conductive layers (dz), and calculating a distance (d), wherein d=√{square root over (dxy2+dz2)}. If the calculated distance d is less than the minimum spacing requirement, a violation is indicated.

Dependencies are inferred from the claim text.