US 2025/0061073 A1 · Interrupt Latency Resilient UART Driver

Abstract

A system and method of reducing data loss in a system utilizing a bus protocol that does not support flow control is disclosed. The peripheral device utilizes a spill buffer which is used to capture any data sent by the host before the peripheral device is able to properly configure the DMA controller. Additionally, the peripheral device includes a recovery routine, which is a software program that parses the spill buffer and extracts any headers or payloads that are contained therein. Using the spill buffer and recovery routine, the baud rate of the bus interface may be increases without incurring any increase in data loss.

Claims18

Dependent claims

A peripheral device to receive data from a host with no flow control, wherein the data comprises a plurality of headers and payloads, the peripheral device comprising:

a processing unit;
a memory device;
and
a DMA controller,
wherein the peripheral device configures the DMA controller to receive a header or a payload and uses an active buffer disposed in the memory device to store the header or payload sent to the peripheral device;
and uses a spill buffer to capture additional headers and payloads transmitted before the DMA controller is properly configured to receive the additional headers and payloads.

3 more elements

Dependencies are inferred from the claim text.

Interrupt Latency Resilient UART Driver

Life of this patent

Interrupt Latency Resilient UART Driver

Life of this patent

Abstract

Claims18