Method and apparatus for shared virtual memory to manage data coherency in a heterogeneous processing system

An apparatus comprising:

• a package device comprising a plurality of integrated circuit (IC) dies, the plurality of IC dies including:
• a central processing unit (CPU) die comprising:
• a plurality of CPU cores to execute instructions of a first instruction set architecture;
• and
• a CPU cache associated with one or more of the CPU cores;
• a graphics processing unit (GPU) die comprising:
• a plurality of GPU cores to execute instructions of a second instruction set architecture;
• and
• a GPU cache associated with one or more of the GPU cores;
• translation circuitry to manage virtual-to-physical address mappings stored in page table structures to access a memory, at least a portion of the virtual-to-physical address mappings comprising shared virtual memory addresses to be shared by the CPU cores and the GPU cores to access the memory at corresponding physical memory addresses;
• and
• a system cache coupled to the CPU cores and the GPU cores, the system cache to store cache line data corresponding to the shared virtual memory addresses,
• wherein both the CPU cores and the GPU cores are to be provided access to the cache line data and wherein a coherency control structure is to be accessed to maintain the cache line data in a coherent state.

A method comprising:

• executing instructions of a first instruction set architecture using a central processing unit (CPU) die, the CPU die including one or more CPU cores and a CPU cache associated with one or more of the CPU cores;
• executing instructions of a second instruction set architecture using a graphics processing unit (GPU) die, the GPU die including one or more GPU cores and a GPU cache associated with one or more of the GPU cores;
• managing virtual-to-physical address mappings stored in page table structures to access a memory, wherein the virtual-to-physical address mappings include shared virtual memory addresses to be shared by the CPU cores and the GPU cores to access the memory at corresponding physical memory addresses;
• and
• accessing a system cache coupled to the CPU cores and the GPU cores to store cache line data corresponding to the shared virtual memory addresses, and providing both the CPU cores and the GPU cores with access to the cache line data to maintain the cache line data in a coherent state using a coherency control structure.

A data processing system comprising:

• a package device comprising a plurality of integrated circuit (IC) dies, the plurality of IC dies including:
• a memory device;
• a central processing unit (CPU) die comprising:
• a plurality of CPU cores to execute instructions of a first instruction set architecture;
• and
• a CPU cache associated with one or more of the CPU cores;
• a graphics processing unit (GPU) die comprising:
• a plurality of GPU cores to execute instructions of a second instruction set architecture;
• and
• a GPU cache associated with one or more of the GPU cores;
• translation circuitry to manage virtual-to-physical address mappings stored in page table structures to access the memory device, at least a portion of the virtual-to-physical address mappings comprising shared virtual memory addresses to be shared by the CPU cores and the GPU cores to access the memory at corresponding physical memory addresses;
• and a system cache coupled to the CPU cores and the GPU cores, the system cache to store cache line data corresponding to the shared virtual memory addresses,
• wherein both the CPU cores and the GPU cores are to be provided access to the cache line data and wherein a coherency control structure is to be accessed to maintain the cache line data in a coherent state.