Hybrid cache coherency
AssigneeMicron Technology, Inc.
InventorTony M. Brewer
Life of this patent
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AssigneeMicron Technology, Inc.
InventorTony M. Brewer
Estimating the term…
To implement a hybrid of software and hardware coherency management, a device can receive an unrestricted-access read request for memory that corresponds to a cache line from a first host and record an indication of the unrestricted-access read request with respect to the cache line. Here, the indication can include an identifier for the first host. However, if the device receives a shared-access read request for the cache line from a second host, the device does not record an identifier of the second host. Rather, the device can communicate an invalidation request for the cache line to the first host using the identifier for the first host to provoke the first host to write-back the data and invalidate the cache line.
A device for hybrid cache coherency, the device comprising:
A method for hybrid cache coherency, the method comprising:
A machine-readable medium including instructions for hybrid cache coherency, the instructions, when executed by processing circuitry of a device, cause the processing circuitry to perform operations comprising:
Dependencies are inferred from the claim text.