Register clearing

A non-transitory computer-readable medium to store computer-readable code for fabrication of an apparatus comprising:

• at least one register rename table structure comprising rename entries for indicating register mappings between architectural registers specified by operations to be processed by processing circuitry and corresponding physical registers provided in hardware;
• and
• register rename circuitry to update the register mappings indicated by the rename entries of the at least one register rename table structure;
• in which:
• rename entries corresponding to at least one set of architectural registers support a cleared-register encoding;
• in response to an operation specifying a source architectural register for which a corresponding rename entry is set to the cleared-register encoding, the register rename circuitry is configured to control the processing circuitry to process that operation with a source operand corresponding to the source architectural register being treated as having a predetermined value;
• and
• in response to detection of a register clearing event indicating that at least one set of architectural registers is to be treated as having been cleared to the predetermined value, the register rename circuitry is configured to set a plurality of rename entries of the at least one register rename table to the cleared-register encoding, the plurality of rename entries corresponding to architectural registers in said at least one set of architectural registers.

A method comprising:

• maintaining at least one register rename table structure comprising rename entries for indicating register mappings between architectural registers specified by operations to be processed by processing circuitry and corresponding physical registers provided in hardware, where rename entries corresponding to at least one set of architectural registers support a cleared-register encoding;
• in response to an operation specifying a source architectural register for which a corresponding rename entry is set to the cleared-register encoding, controlling processing circuitry to process that operation with a source operand corresponding to the source architectural register being treated as having a predetermined value;
• and
• in response to detection of a register clearing event indicating that at least one set of architectural registers is to be treated as having been cleared to the predetermined value, setting a plurality of rename entries of the at least one register rename table to the cleared-register encoding, the plurality of rename entries corresponding to architectural registers in said at least one set of architectural registers.