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US 2025/0040146 A1Published application
Planar ferroelectric memory device
AssigneeKepler Computing Inc.
InventorsSasikanth Manipatruni, Rajeev Kumar Dokania, Ramamoorthy Ramesh, Gaurav Thareja, Amrita Mathuriya
Life of this patent
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Abstract
Approaches for integrating FE memory arrays into a processor, and the resulting structures are described. Simultaneous integrations of regions with ferroelectric (FE) cells and regions with standard interconnects are also described. FE cells include FE capacitors that include a FE stack of layers, which is encapsulated with a protection material. The protection material protects the FE stack of layers as structures for regular logic are fabricated in the same die.
Claims20
An apparatus comprising:
- a transistor, comprising:
- a source;
- a drain;
- a gate electrode between the source and the drain;
- a drain contact coupled with the drain;
- a source contact coupled with the source;
- a gate contact coupled with the gate electrode;
- and
- a first via coupled with the drain contact;
- and
- a structure coupled to the first via, the structure comprising:
- a first etch stop layer (ESL) with a first discontinuity;
- an interlayer dielectric (ILD) over the first ESL, wherein the ILD comprises a second discontinuity, the second discontinuity aligned with the first discontinuity;
- a liner on first sidewalls of the first discontinuity and the second discontinuity, wherein the first sidewalls are sloped;
- a second via electrically coupled with the first via, the second via comprising a fill metal between the liner on the first sidewalls;
- a capacitor on at least a portion of the fill metal, the capacitor comprising:
- a first bottom electrode in contact with the fill metal;
- a second bottom electrode on the first bottom electrode;
- a dielectric layer comprising a ferroelectric or a paraelectric material on the second bottom electrode;
- a first top electrode on the dielectric layer;
- and
- a second top electrode on the first top electrode;
- a second ESL on the ILD, the second ESL adjacent to the first bottom electrode;
- an encapsulation material on second sidewalls of the capacitor, wherein the second sidewalls are vertical;
- and
- a metal contact on the second top electrode.
23 more elements
An apparatus comprising:
- a transistor within a ferroelectric cell region, the transistor comprising:
- a source;
- a drain;
- a gate electrode between the source and the drain;
- a drain contact coupled with the drain;
- a source contact coupled with the source;
- a gate contact coupled with the gate electrode;
- and
- a first via coupled with the drain contact;
- a structure coupled to the first via, the structure comprising:
- an etch stop layer (ESL) with a first discontinuity;
- a first interlayer dielectric (ILD) over the ESL, wherein the first ILD comprises a second discontinuity, the second discontinuity aligned with the first discontinuity;
- a liner on first sidewalls of the first discontinuity and the second discontinuity, wherein the first sidewalls are sloped;
- a second via electrically coupled with the first via, the second via comprising a fill metal between the liner on the first sidewalls;
- a capacitor on at least a first portion of the fill metal, the capacitor comprising:
- a first bottom electrode in contact with the fill metal;
- a second bottom electrode on the first bottom electrode;
- a non-linear dielectric layer comprising a ferroelectric or a paraelectric material on the second bottom electrode;
- a first top electrode on the non-linear dielectric layer;
- and
- a second top electrode on the first top electrode;
- an encapsulation material comprising a second portion on second sidewalls of the capacitor, wherein the second sidewalls are vertical;
- a metal contact on the second top electrode;
- and
- a plate line coupled with the metal contact;
- and
- a second structure within a logic region, the second structure comprising:
- a third via comprising the fill metal within a third discontinuity in the ESL and within a fourth discontinuity in the first ILD;
- and
- a fourth via within a fifth discontinuity in a second ILD, wherein the fifth discontinuity is substantially aligned and over the fourth discontinuity, and wherein the second ILD is above the first ILD.
27 more elements
A system comprising:
- a processor circuitry to execute one or more instructions;
- a communication interface communicatively coupled to the processor circuitry;
- and
- a memory to store the one or more instructions, wherein the processor circuitry or the memory includes an apparatus comprising:
- a transistor within a ferroelectric cell region, the transistor comprising:
- a source;
- a drain;
- a gate electrode between the source and the drain;
- a drain contact coupled with the drain;
- a source contact coupled with the source;
- a gate contact coupled with the gate electrode;
- and
- a first via coupled with the drain contact;
- a structure coupled to the first via, the structure comprising:
- an etch stop layer (ESL) with a first discontinuity;
- a first interlayer dielectric (ILD) over the ESL, wherein the first ILD comprises a second discontinuity, the second discontinuity aligned with the first discontinuity;
- a liner on first sidewalls of the first discontinuity and the second discontinuity, wherein the first sidewalls are sloped;
- a second via electrically coupled with the first via, the second via comprising a fill metal between the liner on the first sidewalls;
- a capacitor on at least a first portion of the fill metal, the capacitor comprising:
- a first bottom electrode in contact with the fill metal;
- a second bottom electrode on the first bottom electrode;
- a non-linear dielectric layer comprising a ferroelectric or a paraelectric material on the second bottom electrode;
- a first top electrode on the non-linear dielectric layer;
- and
- a second top electrode on the first top electrode;
- an encapsulation material comprising a second portion on second sidewalls of the capacitor, wherein the second sidewalls are vertical;
- a metal contact on the second top electrode;
- and
- a plate line coupled with the metal contact;
- and
- a second structure within a logic region, the second structure comprising:
- a third via comprising the fill metal within a third discontinuity in the ESL and within a fourth discontinuity in the first ILD;
- and
- a fourth via within a fifth discontinuity in a second ILD, wherein the fifth discontinuity is substantially aligned and over the fourth discontinuity, and wherein the second ILD is above the first ILD.
31 more elements
Dependencies are inferred from the claim text.