Image sensor

An image sensor, comprising:

• a first semiconductor chip including
• a first semiconductor substrate having a first region including a plurality of pixels arranged therein and a second region around the first region,
• a first wiring structure on a lower surface of the first semiconductor substrate, and
• a first bonding pad exposed to a lower surface of the first wiring structure;
• a second semiconductor chip including
• a second semiconductor substrate having an upper surface including devices configured to form a pixel signal generator circuit,
• a second wiring structure on the upper surface of the second semiconductor substrate and having an upper surface bonded to a lower surface of the first wiring structure,
• a second upper bonding pad exposed to the upper surface of the second wiring structure and bonded to the first bonding pad,
• a back side insulating layer on a lower surface of the second semiconductor substrate,
• a conductive through-via penetrating through the back side insulating layer and the second semiconductor substrate and electrically connected to the second wiring structure, and
• a shielding metal pattern buried in the back side insulating layer;
• a bonding layer including
• a bonding insulating layer on the back side insulating layer, and
• a lower bonding pad exposed to a lower surface of the bonding insulating layer and connected to the conductive through-via;
• and
• a third semiconductor chip including
• a third semiconductor substrate having an upper surface including logic devices,
• a third wiring structure on the upper surface of the third semiconductor substrate and having an upper surface bonded to the lower surface of the bonding insulating layer, and
• a third bonding pad exposed to the upper surface of the third wiring structure and bonded to the lower bonding pad.

An image sensor, comprising:

• a first semiconductor chip including
• a first semiconductor substrate having a first region including a plurality of pixels arranged therein and a second region around the first region,
• a first wiring structure on a lower surface of the first semiconductor substrate, and
• a first bonding pad exposed to a lower surface of the first wiring structure;
• a second semiconductor chip including
• a second semiconductor substrate having upper surface including devices configured to form a pixel signal generator circuit,
• a second wiring structure on an upper surface of the second semiconductor substrate and having an upper surface bonded to the lower surface of the first wiring structure,
• an upper bonding pad exposed to an upper surface of the second wiring structure and bonded to the first bonding pad,
• a first back side insulating layer on a lower surface of the second semiconductor substrate, and
• a conductive through-via penetrating through regions overlapping the second region of the first back side insulating layer and the second semiconductor substrate and electrically connected to the second wiring structure;
• a shielding structure layer including
• a shielding metal pattern on a region overlapping the first region of the first back side insulating layer,
• a connection pattern connected to the conductive through-via on the first back side insulating layer, and
• a second back side insulating layer surrounding the shielding metal pattern and the connection pattern on the first back side insulating layer;
• a bonding layer including
• a bonding insulating layer on the second back side insulating layer, and
• a lower bonding pad exposed to a lower surface of the bonding insulating layer and connected to the conductive through-via through the connection pattern;
• and
• a third semiconductor chip including
• a third semiconductor substrate having one surface including logic devices,
• a third wiring structure on an upper surface of the third semiconductor substrate, having an upper surface bonded to the lower surface of the bonding insulating layer, and having a third wiring layer, and
• a third bonding pad bonded to the lower bonding pad and connected to the third wiring layer.