3d-stacked semiconductor device manufactured using channel spacer
AssigneeSamsung Electronics Co., Ltd.
InventorsSeungchan YUN, Jaejik Baek, Kang-ill Seo
Life of this patent
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Abstract
Provided is a three-dimension (3D) stacked semiconductor device which includes: a 1stsource/drain region connected to a 1st channel structure; and a 2nd source/drain region, above the 1st source/drain region, connected to a 2nd channel structure above the 1st channel structure, wherein the 2nd channel structure has a smaller length than the 1st channel structure in a channel-length direction, in which the 2nd source/drain region is connected to a 3rd source/drain region through the 2nd channel structure.
Claims21
A three-dimension (3D) stacked semiconductor device comprising:
- a 1st source/drain region connected to a 1st channel structure;
- and
- a 2nd source/drain region, above the 1st source/drain region, connected to a 2nd channel structure above the 1st channel structure,
- wherein the 2nd channel structure has a smaller length than the 1st channel structure in a channel-length direction, in which the 2nd source/drain region is connected to a 3rd source/drain region through the 2nd channel structure.
The 3D-stacked semiconductor device of claim 2, further comprising:
- a gate structure surrounding the 1st channel structure and the 2nd channel structure;
- a 1st inner spacer between a 1st portion of the gate structure and the 1st source/drain region;
- and
- a 2nd inner spacer between a 2nd portion of the gate structure and the 2nd source/drain region,
- wherein the 2nd inner spacer has a smaller length than the 1st inner spacer in the channel-length direction.
A three-dimension (3D) stacked semiconductor device comprising:
- a 1st source/drain region connected to a 1st channel structure;
- and
- a 2nd source/drain region, above the 1st source/drain region, connected to a 2nd channel structure above the 1st channel structure,
- wherein the 2nd source/drain region has a greater length than the 1st source/drain region in a channel-length direction, in which the 2nd source/drain region is connected to a 3rd source/drain region through the 2nd channel structure.
A three-dimension (3D) stacked semiconductor device comprising:
- a 1st source/drain region connected to a 1st channel structure;
- a 2nd source/drain region, above the 1st source/drain region, connected to a 2nd channel structure above the 1st channel structure;
- a gate structure surrounding the 1st channel structure and the 2nd channel structure;
- a 1st inner spacer between a 1st portion of the gate structure and the 1st source/drain region;
- and
- a 2nd inner spacer between a 2nd portion of the gate structure and the 2nd source/drain region,
- wherein the 2nd inner spacer has a smaller length than the 1st inner spacer in a channel-length direction, in which the 2nd source/drain region is connected to a 3rd source/drain region through the 2nd channel structure.
21-23. (canceled)
Dependencies are inferred from the claim text.