Method for fabricating a semiconductor structure

Abstract

A method for fabricating a semiconductor structure is disclosed. A substrate having a dielectric layer thereon and a gate trench formed in the dielectric layer is prepared. The substrate is subjected to a physical vapor deposition (PVD) process in a physical vapor deposition chamber equipped with an auto capacitance tuner to conformally deposit a metal layer on a top surface of the dielectric layer and on an interior surface of the gate trench. The PVD process comprises: (i) tuning the auto capacitance tuner to provide positive radio frequency (RF) bias to the substrate in the PVD chamber for a first time period; and (ii) subsequently tuning the auto capacitance tuner to provide negative RF bias to the substrate in the PVD chamber for a second time period.

Dependencies are inferred from the claim text.