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US 2025/0031406 A1Published application
High voltage semiconductor device and manufacturing method thereof
AssigneeSK keyfoundry Inc.
InventorHanseob CHA
Life of this patent
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Abstract
A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes: a first conductive type buried layer disposed on a substrate; a first conductive type deep well region, a second conductive type body region, and a first conductive type drift region which are disposed on the first conductive type buried layer; a source region disposed in the second conductive type body region; a drain region disposed in the first conductive type deep well region; and a gate electrode disposed on the second conductive type body region and the first conductive type drift region.
Claims15
A semiconductor device, comprising:
- a first buried layer having a first conductive type disposed on a substrate, the first buried layer comprising a first region, a second region, and a third region;
- a first deep well region having the first conductive type disposed on the second region of the first buried layer;
- a second deep well region having the first conductive type disposed on the third region of the first buried layer;
- a second buried layer having a second conductive type overlapping the first deep well region;
- a third buried layer having the second conductive type overlapping the second deep well region;
- a body region having the second conductive type disposed between the second buried layer and the third buried layer, the body region being in direct contact with the second buried layer and the third buried layer;
- a first drift region having the first conductive type disposed on the second buried layer;
- a second drift region having the first conductive type disposed on the third buried layer;
- a source region disposed in the body region;
- a first drain region disposed adjacent to the first drift region;
- a second drain region disposed adjacent to the second drift region;
- a first gate electrode disposed between the source region and the first drain region;
- and
- a second gate electrode disposed between the source region and the second drain region.
11 more elements
A semiconductor device manufacturing method, the method comprising:
- providing a substrate;
- forming a first buried layer having a first conductive type on the substrate, the first buried layer comprising a first region, a second region, and a third region;
- forming a first deep well region having the first conductive type on the second region of the first buried layer;
- forming a second deep well region having the first conductive type on the third region of the first buried layer;
- forming a second buried layer having a second conductive type overlapping the first deep well region;
- forming a third buried layer having the second conductive type overlapping the second deep well region;
- forming a first drift region having the first conductive type on the second buried layer;
- forming a second drift region having the first conductive type on the third buried layer;
- forming a body region having the second conductive type between the second buried layer and the third buried layer;
- forming a source region in the body region;
- forming a first drain region adjacent to the first drift region;
- forming a second drain region adjacent to the second drift region;
- forming a first gate electrode between the source region and the first drain region;
- and
- forming a second gate electrode between the source region and the second drain region,
- wherein the body region is in direct contact with the second buried layer and the third buried layer.
13 more elements
A semiconductor device, comprising:
- a substrate;
- a first layer doped with N-type dopants and disposed on the substrate;
- a second layer doped with P-type dopants and disposed on the first layer;
- a third layer doped with the P-type dopants and disposed on the first layer;
- a body region disposed between the second layer and the third layer, wherein each of the second layer and the third layer is in direct contact with the body region;
- a first drift region and a second drift region disposed on the second layer and the third layer, respectively;
- a first deep well region overlapping the second layer;
- a second deep well region overlapping the third layer;
- a first gate electrode arranged to overlap the body region, the first drift region, and the second layer;
- a second gate electrode arranged to overlap the body region, the second drift region, and the third layer;
- a first drain region disposed in the first deep well region;
- a second drain region disposed in the second deep well region;
- a source region disposed in the body region;
- a first deep trench disposed adjacent to the first drain region;
- and
- a second deep trench disposed adjacent to the second drain region,
- wherein the source region is spaced apart from the first deep trench and the second deep trench.
14 more elements
Dependencies are inferred from the claim text.