Three dimensional chip architecture
OwnerRavi Shankar Agarwal, Mahesh Srinivasa Maddury +1inventors
InventorsRavi Shankar Agarwal, Mahesh Srinivasa Maddury, Harikrishna Madadi Reddy
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Abstract
Three-dimensional chip architecture is described herein. In one example aspect, an integrated circuit may include an interposer layer. The integrated circuit may further include a plurality of random access memory chiplets stacked atop the interposer layer, and a plurality of compute chiplets. The plurality of compute chiplets may be stacked atop a respective random access memory chip of the plurality of random access memory chiplets, such that the plurality of compute chiplets may be in electrical communication with the respective random access memory chip of the plurality of random access memory chiplets.
Claims20
An integrated circuit comprising:
- an interposer layer;
- a plurality of random access memory chiplets stacked atop the interposer layer;
- and
- a plurality of compute chiplets, wherein the plurality of compute chiplets are stacked atop a respective random access memory chip of the plurality of random access memory chiplets, such that the plurality of compute chiplets are in electrical communication with the respective random access memory chip of the plurality of random access memory chiplets.
A method comprising:
- transmitting at least one electrical signal from a computing chiplet;
- and
- transferring the at least one electrical signal to a random access memory chiplet, wherein the computing chiplet is stacked atop the random access memory chiplet, thereby forming a three-dimensional stacked integrated circuit.
A non-transitory computer-readable medium storing instructions that, when executed, cause:
- transmitting at least one electrical signal from a computing chiplet;
- and
- transferring the at least one electrical signal to a random access memory chiplet, wherein the computing chiplet is stacked atop the random access memory chiplet, thereby forming a three-dimensional stacked integrated circuit.
Dependencies are inferred from the claim text.