US 2025/0031380 A1 · 3T MEMORY WITH ENHANCED SPEED OF OPERATION AND DATA RETENTION

Abstract

A memory device including a plurality of memory cells, at least one of the plurality of memory cells includes a first transistor, a second transistor, and a third transistor. The first transistor includes a first drain/source path and a first gate structure electrically coupled to a write word line. The second transistor includes a second drain/source path and a second gate structure electrically coupled to the first drain/source path of the first transistor. The third transistor includes a third drain/source path electrically coupled to the second drain/source path of the second transistor and a third gate structure electrically coupled to a read word line. Where, the first transistor, and/or the second transistor, and/or the third transistor is a ferroelectric field effect transistor or a negative capacitance field effect transistor.

Claims20

Dependent claims

A method of manufacturing a memory device, comprising:

forming a first fin structure in a first direction on a substrate;
disposing a first gate structure including a first ferroelectric material on the first fin structure in a second direction that is non-parallel to the first direction to form a first transistor;
disposing a second gate structure on the first fin structure in the second direction to form a second transistor, the second gate structure spaced apart from the first gate structure on the first fin structure;
forming a second fin structure in the first direction on the substrate, the second fin structure spaced apart from the first fin structure on the substrate;
and
disposing a third gate structure including a second ferroelectric material on the second fin structure in the second direction to form a third transistor.

3 more elements

A method of manufacturing a memory device, comprising:

forming a first fin structure in a first direction on a substrate;
forming a second fin structure in the first direction on the substrate, the second fin structure spaced apart from the first fin structure in a second direction that is non-parallel to the first direction on the substrate;
disposing a first gate structure including a first ferroelectric material in the second direction on the first fin structure to form a first transistor, the first gate structure connected to the second fin structure;
disposing a second gate structure on the first fin structure in the second direction to form a second transistor;
and
disposing a third gate structure on the second fin structure in the second direction to form a third transistor,
wherein forming the first fin structure and disposing the first gate structure includes:
depositing a hard mask on the substrate;
forming a mandrel on the hard mask;
forming a spacer along sides of the mandrel and on the hard mask;
etching away portions of the hard mask and the substrate to form one or more fins;
depositing shallow trench isolation material on slanted portions of the one or more fins;
disposing a dummy gate over channel regions of the one or more fins and over the shallow trench isolation material;
forming drain/source epitaxial regions on the one or more fins;
forming gate spacers on each side of the dummy gate and on the drain/source epitaxial regions;
disposing the first gate structure that includes the first ferroelectric material on the first fin structure by replacing the dummy gate with the first gate structure;
and
forming an interlayer dielectric adjacent the gate spacers and over the drain/source epitaxial regions.

15 more elements

A method of manufacturing a memory device, comprising:

forming a first fin structure in a first direction on a substrate;
forming a second fin structure in the first direction on the substrate, the second fin structure spaced apart from the first fin structure in a second direction that is non-parallel to the first direction on the substrate,
wherein forming each of the first fin structure and the second fin structure includes:
depositing a hard mask on the substrate;
forming a mandrel on the hard mask;
forming a spacer along sides of the mandrel and on the hard mask;
etching away portions of the hard mask and the substrate to form one or more fins;
depositing shallow trench isolation material on slanted portions of the one or more fins;
disposing one or more dummy gates over channel regions of the one or more fins and over the shallow trench isolation material;
forming drain/source epitaxial regions on the one or more fins;
and
forming gate spacers on each side of the one or more dummy gates and on the drain/source epitaxial regions;
disposing a first gate structure including a first ferroelectric material in the second direction on the first fin structure by replacing the one or more dummy gates with the first gate structure to form a first transistor, the first gate structure connected to the second fin structure;
disposing a second gate structure on the first fin structure in the second direction to form a second transistor;
and
disposing a third gate structure on the second fin structure in the second direction to form a third transistor.

13 more elements

Dependencies are inferred from the claim text.

3t memory with enhanced speed of operation and data retention

Life of this patent

3t memory with enhanced speed of operation and data retention

Life of this patent

Abstract

Claims20