3d semiconductor memory device

A three-dimensional (3D) semiconductor memory device comprising:

• a memory cell region;
• and
• a peripheral circuit configured to control the memory cell region,
• wherein the memory cell region comprises:
• a cell array region comprising a plurality of memory cells arranged along a vertical direction;
• and
• a connection region comprising ends of a plurality of word lines that are connected to the plurality of memory cells,
• wherein the peripheral circuit comprises a peripheral circuit region overlapping the connection region along the vertical direction,
• wherein the peripheral circuit region comprises a plurality of main pass transistors electrically connected to the plurality of word lines, and a plurality of dummy pass transistors electrically separated from the plurality of word lines, and
• wherein the plurality of main pass transistors is arranged along a first direction perpendicular to the vertical direction.

A three-dimensional (3D) semiconductor memory device comprising:

• a memory cell region;
• and
• a peripheral circuit region configured to control the memory cell region,
• wherein the memory cell region comprises a plurality of blocks,
• wherein each of the plurality of blocks comprises a cell array region comprising:
• a plurality of memory cells arranged along a vertical direction;
• and
• a connection region comprising ends of a plurality of word lines that are connected to the plurality of memory cells,
• wherein the peripheral circuit region comprises peripheral circuit regions overlapping, respectively, with the connection region of the plurality of blocks,
• wherein each of the peripheral circuit regions comprises a plurality of main pass transistors electrically connected to the plurality of word lines, and a plurality of dummy pass transistors electrically separated from the plurality of word lines, and
• wherein the plurality of main pass transistors is arranged along a first direction perpendicular to the vertical direction.