Semiconductor devices including stack structure having gate region and insulating region

A semiconductor device, comprising:

• a peripheral circuit structure;
• a stack structure in a memory cell array region and extending into a connection region, wherein the stack structure vertically overlaps the peripheral circuit structure and includes a gate region and an insulating region;
• a capping insulating layer on the stack structure;
• and
• a vertical memory structure penetrating the gate region in the memory cell array region,
• wherein the stack structure has a staircase structure in the connection region,
• wherein the gate region is in the memory cell array region and extends into the connection region,
• wherein the insulating region is in the connection region,
• wherein the gate region of the stack structure includes interlayer insulating layers and conductive layers alternately stacked in a vertical direction,
• wherein the insulating region of the stack structure includes first insulating layers and second insulating layers alternately stacked in the vertical direction,
• wherein a material of the first insulating layers is different from a material of the second insulating layers,
• wherein the second insulating layers include insulating pads contacting the capping insulating layer,
• wherein the insulating pads include a first pad and a second pad,
• wherein the first pad is at a different level from the second pad,
• wherein the first pad includes a first portion, a second portion, and a third portion between the first portion and the second portion,
• wherein the first portion, the third portion, and the second portion are sequentially arranged in a first direction, and
• wherein a thickness of each of the first and second portions is greater than a thickness of the third portion.