Circuit with a phase locked loop with disturbance responses

A circuit comprising:

• a phase locked loop circuit that includes:
• a phase frequency detector configured to:
• receive a reference clock and a feedback clock;
• and
• determine a phase error based on the reference clock and the feedback clock;
• a loop filter coupled to the phase frequency detector and configured to provide a clock control signal based on the phase error;
• and
• an oscillator coupled to the loop filter and configured to provide a clock signal based on the clock control signal, wherein the feedback clock is based on the clock signal, and wherein the phase locked loop circuit is configured to provide an output clock based on the clock signal;
• and
• a controller coupled to the phase locked loop circuit and configured to:
• receive the phase error;
• detect a behavior of the phase error;
• and
• responsive to the behavior of the phase error, perform a response that includes:
• causing the phase frequency detector to adjust the phase error;
• and
• causing the loop filter to adjust the clock control signal.

A method comprising:

• receiving a phase error with respect to a reference clock and a feedback clock, wherein:
• the phase error is determined by a phase frequency detector;
• and
• the feedback clock is generated based on an output of a loop filter;
• detecting whether a behavior of the phase error is present;
• and
• based on whether the behavior is present, determine whether to perform a response that includes:
• causing the phase frequency detector to adjust the phase error;
• and
• causing the loop filter to adjust the output of the loop filter.