Semiconductor package having an inorganic layer on a mold layer and method of fabricating the same

A semiconductor package comprising:

• a buffer die;
• a plurality of memory dies stacked on the buffer die;
• a mold layer that covers a portion of a top surface of the buffer die and lateral surfaces of the plurality of memory dies;
• and
• an inorganic layer disposed on the mold layer,
• wherein the buffer die includes:
• a first through via;
• and
• a plurality of external connection members disposed on a lower portion of the buffer die,
• wherein the memory dies include first to fourth memory dies that are sequentially stacked on the buffer die,
• wherein each of the first to third memory dies includes a second through via,
• wherein the inorganic layer covers at least a portion of the lateral surface of the fourth memory die,
• wherein a top surface of the inorganic layer and a top surface of the fourth memory die are substantially coplanar with each other,
• wherein a thermal conductivity of the inorganic layer is greater than a thermal conductivity of the mold layer,
• wherein a stiffness of the inorganic layer is greater than a stiffness of the mold layer,
• wherein a lateral surface of the inorganic layer and a lateral surface of the mold layer are vertically aligned with each other,
• wherein a thickness of the inorganic layer is in a range of about 2 μm to about 10 μm, and
• wherein the inorganic layer includes SiO2.

A semiconductor package, comprising:

• a package substrate;
• an interposer substrate disposed on the package substrate;
• a first semiconductor chip, a second semiconductor chip, and a third semiconductor chip that are disposed on the interposer substrate;
• a first mold layer that covers a portion of the interposer substrate and the first, second, and third semiconductor chips;
• and
• an inorganic layer disposed on the first mold layer,
• wherein each of the first and third semiconductor chips includes:
• a buffer die;
• a plurality of memory dies stacked on the buffer die;
• and
• a second mold layer that covers the buffer die and the memory dies,
• wherein a top surface of the inorganic layer is substantially coplanar with a top surface of each of the first, second, and third semiconductor chips,
• wherein the inorganic layer includes oxide or nitride, and
• wherein a thermal conductivity of the inorganic layer is greater than a thermal conductivity of each of the first and second mold layers.