Method of manufacturing semiconductor structure and semiconductor structure thereof

A method for manufacturing a semiconductor structure, comprising:

• receiving a circuit layout, that includes a circuit pattern, a mark pattern, and a dummy pattern to be formed on a same material layer over an integrated circuit (IC) substrate, wherein the circuit pattern is distant from the mark pattern, and the dummy pattern is proximal to and at least partially between different portions of the mark pattern;
• removing the dummy pattern from the circuit layout;
• and
• generating a modified circuit layout for circuit fabrication without the dummy pattern.

A semiconductor structure, comprising:

• a substrate, including a cell region, a peripheral region surrounding the cell region, and a logo region in the peripheral region;
• a first metal layer, disposed over the substrate and comprising:
• a first conductive feature in the cell region;
• a second conductive feature in the logo region, wherein the second conductive feature is recognizable as a first identification mark;
• and
• a third conductive feature in the logo region adjacent to the second conductive feature, wherein the third conductive feature is disposed between different portions of the second conductive feature and configured as a dummy pattern;
• and
• a second metal layer, disposed over the first metal layer and comprising:
• a fourth conductive feature in the cell region, electrically connected to the first conductive feature;
• a fifth conductive feature in the logo region, overlapping the second conductive feature, wherein the fifth conductive feature is recognizable as a second identification mark;
• and
• a dielectric layer, surrounding the fifth conductive feature, wherein the second metal layer in the logo region consists of the fifth conductive feature and the dielectric layer.