Semiconductor package and methods of forming the same

A semiconductor package, comprising:

• a package substrate;
• a semiconductor chip mounted on the package substrate;
• and
• one or more outer terminals provided below the package substrate,
• wherein the package substrate comprises:
• an insulating portion;
• a plurality of first pads provided on a top surface of the insulating portion, the semiconductor chip being mounted on the plurality of first pads;
• a plurality of second pads and a third pad provided on a bottom surface of the insulating portion and coupled to the one or more outer terminals;
• one or more interconnection patterns provided in the insulating portion to connect the plurality of first pads to the plurality of second pads;
• and
• a heat-dissipation pattern disposed in the insulating portion and on the third pad,
• wherein the heat-dissipation pattern comprises at least one conductive pattern and at least one thermoelectric pattern, vertically and alternately stacked on the third pad,
• wherein the at least one conductive pattern comprises a same material as the one or more interconnection patterns, and
• wherein an end portion of the heat-dissipation pattern residing adjacent to the semiconductor chip is configured to be cooled when a voltage is applied to the third pad.

A semiconductor package, comprising:

• a package substrate;
• an interposer substrate disposed on the package substrate;
• a first semiconductor chip mounted on the interposer substrate;
• and
• a chip stack provided on the interposer substrate and spaced apart from the first semiconductor chip, the chip stack comprising a plurality of second semiconductor chips vertically stacked on the interposer substrate,
• wherein the interposer substrate comprises:
• one or more interconnection patterns configured to deliver an operation signal from the package substrate to the first semiconductor chip and the chip stack;
• one or more heat-dissipation patterns configured to deliver electrical power from the package substrate to the first semiconductor chip or the chip stack, the one or more heat-dissipation patterns comprising at least one conductive pattern and at least one thermoelectric pattern, alternately connected in series in a direction perpendicular relative to the interposer substrate;
• and
• a capacitor pattern electrically connected to the at least one conductive pattern,
• wherein the at least one conductive pattern comprises a same material as the one or more interconnection patterns, and
• wherein the at least one thermoelectric pattern comprises an n-type semiconductor material.