Flash memory array, and writing method and erasing method therefor

A writing method of a flash memory array, wherein the flash memory array comprises:

• a plurality of flash memory cells arranged in a row direction and a column direction perpendicular to the row direction;
• a plurality of word line sets extending in the row direction;
• and
• a plurality of bit line sets extending in the column direction,
• wherein a flash memory cell pair is disposed at an intersection of the word line set and the bit line set, and the flash memory cell pair includes a first flash memory cell and a second flash memory cell adjacent in the row direction and sharing the same bit line set,
• wherein each of the first flash memory cell and the second flash memory cell includes a first storage transistor, a selection transistor, and a second storage transistor sequentially connected in series in the column direction,
• wherein, in each of the first flash memory cell and the second flash memory cell, a source region of the first storage transistor is connected to a first electrode of the flash memory cell, and a drain region of the second storage transistor is connected to a second electrode of the flash memory cell,
• wherein each bit line set includes a first bit line, a middle bit line, and a second bit line, the first bit line is connected to the first electrode of the first flash memory cell of the flash memory cell pair, the second bit line is connected to the second electrode of the second flash memory cell of the flash memory cell pair, and the middle bit line is connected to the second electrode of the first flash memory cell and the first electrode of the second flash memory cell, and
• wherein each word line set includes a first control line, a word line and a second control line extending along the row direction, the first control line is connected to a gate electrode of the first storage transistor, the word line is connected to a gate electrode of the selection transistor, and the second control line is connected to a gate electrode of the second storage transistor,
• the writing method comprising:
• performing a write operation on the first storage transistor of the first flash memory cell by applying a first writing voltage to the first bit line, applying a second writing voltage to the middle bit line and the second bit line, applying a third writing voltage to the first control line, applying a fourth writing voltage to the word line, and applying a fifth writing voltage to the second control line;
• performing a write operation on the second storage transistor of the first flash memory cell by applying the second writing voltage to the first bit line, applying the first writing voltage to the middle bit line and the second bit line, applying the fifth writing voltage to the first control line, applying the fourth writing voltage to the word line, and applying the third writing voltage to the second control line;
• performing a write operation on the first storage transistor of the second flash memory cell by applying the first writing voltage to the first bit line and the middle bit line, applying the second writing voltage to the second bit line, applying the third writing voltage to the first control line, applying the fourth writing voltage to the word line, and applying the fifth writing voltage to the second control line;
• and
• performing a write operation on the second storage transistor of the second flash memory cell by applying the second writing voltage to the first bit line and the middle bit line, applying the first writing voltage to the second bit line, applying the fifth writing voltage to the first control line, applying the fourth writing voltage to the word line, and applying the third writing voltage to the second control line,
• wherein the fourth writing voltage is equal to or lower than a first power voltage, the second writing voltage is equal to or higher than a second power voltage, the first writing voltage is higher than a preset voltage, and the third writing voltage is higher than the first writing voltage,
• wherein the first power voltage is higher than the second power voltage,
• wherein the preset voltage is predetermined based on a carrier barrier height at an interface between a substrate and gate dielectric stacks of the first storage transistor and the second storage transistor,
• wherein the first writing voltage, the fourth writing voltage, and the fifth writing voltage are higher than the second writing voltage,
• wherein the second writing voltage is connected to the second power voltage through a constant current load, and
• wherein, during a writing operation of a flash memory cell, the first writing voltage, the second writing voltage, the third writing voltage, the fourth writing voltage, and the fifth writing voltage turn on all the first storage transistor, the second storage transistor, and the selection transistor of the flash memory cell.

An erasing method of the flash memory array, wherein the flash memory array comprises:

• a plurality of flash memory cells arranged in a row direction and a column direction perpendicular to the row direction;
• a plurality of word line sets extending in the row direction;
• and
• a plurality of bit line sets extending in the column direction,
• wherein a flash memory cell pair is disposed at an intersection of the word line set and the bit line set, and the flash memory cell pair includes a first flash memory cell and a second flash memory cell adjacent in the row direction and sharing the same bit line set,
• wherein each of the first flash memory cell and the second flash memory cell includes a first storage transistor, a selection transistor, and a second storage transistor sequentially connected in series in the column direction,
• wherein, in each of the first flash memory cell and the second flash memory cell, a source region of the first storage transistor is connected to a first electrode of the flash memory cell, and a drain region of the second storage transistor is connected to a second electrode of the flash memory cell,
• wherein each bit line set includes a first bit line, a middle bit line, and a second bit line, the first bit line is connected to the first electrode of the first flash memory cell of the flash memory cell pair, the second bit line is connected to the second electrode of the second flash memory cell of the flash memory cell pair, and the middle bit line is connected to the second electrode of the first flash memory cell and the first electrode of the second flash memory cell, and
• wherein each word line set includes a first control line, a word line and a second control line extending along the row direction, the first control line is connected to a gate electrode of the first storage transistor, the word line is connected to a gate electrode of the selection transistor, and the second control line is connected to a gate electrode of the second storage transistor,
• the erasing method comprising a first erasing step of:
• performing an erasing operation on the first storage transistors of the first flash memory cell and the second flash memory cell by applying a first erasing voltage to the first bit line, the middle bit line, and the second bit line, applying a second erasing voltage to the first control line, and applying a second power voltage to the word line and the second control line or floating the word line and the second control line;
• and
• performing an erasing operation on the second storage transistors of the first flash memory cell and the second flash memory cell by applying the first erasing voltage to the first bit line, the middle bit line, and the second bit line, applying the second power voltage to the word line and the first control line or floating the word line and the first control line, and applying the second erasing voltage to the second control line,
• wherein the first erasing voltage is higher than a preset voltage, and the second erasing voltage is equal to or lower than the second power voltage, and
• wherein the preset voltage is predetermined based on a carrier barrier height at an interface between a substrate and gate dielectric stacks of the first storage transistor and the second storage transistor.