Hardware supported multiply-accumulate (mac) operation in a reconfigurable parallel processor

A processor, comprising:

• a memory unit;
• and
• a plurality of columns of vector processing units coupled to the memory unit, each column of the vector processing units comprising a memory port (MP) configured for vector data access operations and a processing element (PE) having a vector Arithmetic Logic Unit (ALU) configured for vector data processing, the MP of each column of the vector processing units comprising:
• an input buffer to store a first matrix loaded from the memory unit;
• and
• a vector multiply-add (MAD) unit that contains a plurality of MAD units, each MAD unit of the plurality of MAD units comprising:
• a first input coupled to one of storage units of the input buffer holding a row of the first matrix,
• a second input coupled to the memory unit to load a second matrix from the memory unit, and
• a plurality of multipliers and a multiple-input adder,
• wherein the plurality of multipliers are configured to generate a set of multiplication results with each multiplication result being generated by multiplying an element of a row of the first matrix and a corresponding element of the second matrix,
• wherein the vector MAD unit is configured to generate a vector of MAD results with each multiple-input adder configured to generate a MAD result of the vector of MAD results by adding all multiplication results of the set of multiplication results generated by the plurality of multipliers of a same MAD unit as the respective multiple-input adder;
• and
• wherein the MP is configured to output the vector of MAD results as a vector input to the vector ALU of a PE of a same column as the MP.