Automated circuit generation

A computer system for automatically generating a transistor level circuit schematic for an integrated circuit comprising:

• one or more processors;
• and
• a non-transitory computer-readable storage medium having stored thereon computer executable instructions, which when executed by the computer system, cause the computer system to perform a method comprising:
• storing a plurality of sets of predefined transistor level sub-circuit schematics, the plurality of sets of predefined transistor level sub-circuit schematics comprising analog circuits, each set of predefined transistor level sub-circuit schematics corresponding to one of a plurality of functional circuit components;
• receiving a plurality of parameters;
• determining from the plurality of parameters, a plurality of subsets of predefined transistor level sub-circuit schematics from the plurality of sets of predefined transistor level sub-circuit schematics;
• generating a circuit specification, wherein the circuit specification specifies electrical combinations of the plurality of subsets of predefined transistor level sub-circuit schematics;
• and
• retrieving the plurality of subsets of predefined transistor level sub-circuit schematics based on the circuit specification;
• and
• combining the plurality of subsets of predefined transistor level sub-circuit schematics to form said transistor level schematic of the integrated circuit.

A non-transitory computer-readable storage medium having stored thereon computer executable instructions, which when executed by a computer system, cause the computer system to:

• storing a plurality of sets of predefined transistor level sub-circuit schematics, the plurality of sets of predefined transistor level sub-circuit schematics comprising analog circuits, each set of predefined transistor level sub-circuit schematics corresponding to one of a plurality of functional circuit components;
• receiving a plurality of parameters;
• determining from the plurality of parameters, a plurality of subsets of predefined transistor level sub-circuit schematics from the plurality of sets of predefined transistor level sub-circuit schematics;
• generating a circuit specification, wherein the circuit specification specifies electrical combinations of the plurality of subsets of predefined transistor level sub-circuit schematics;
• and
• retrieving the plurality of subsets of predefined transistor level sub-circuit schematics based on the circuit specification;
• and
• combining the plurality of subsets of predefined transistor level sub-circuit schematics to form said transistor level schematic of the integrated circuit.

A computer system for automatically generating a transistor level circuit schematic for an integrated circuit comprising:

• a library storing, by at least one software system executing on at least one computer, a plurality of sets of predefined transistor level sub-circuit schematics, the plurality of sets of predefined transistor level sub-circuit schematics comprising analog circuits, each set of predefined transistor level sub-circuit schematics corresponding to one of a plurality of functional circuit components;
• means for receiving, by the at least one software system executing on at least one computer, a plurality of parameters;
• means for determining, by the at least one software system executing on at least one computer, from the plurality of parameters, a plurality of subsets of predefined transistor level sub-circuit schematics from the plurality of sets of predefined transistor level sub-circuit schematics;
• means for generating, by the at least one software system executing on at least one computer, a circuit specification, wherein the circuit specification specifies electrical combinations of the plurality of subsets of predefined transistor level sub-circuit schematics;
• and
• means for retrieving, by the at least one software system executing on at least one computer, the plurality of subsets of predefined transistor level sub-circuit schematics based on the circuit specification;
• and
• means for combining, by the at least one software system executing on at least one computer, the plurality of subsets of predefined transistor level sub-circuit schematics to form said transistor level schematic of the integrated circuit.