US 2024/0405121 A1Published application

Split gate mosfet and manufacturing method thereof

AssigneeMosel Vitelic, Inc.

InventorsChia-Ming Kou, Cin-Hua Jheng, Wen-Wei Shih, Cheng-Wei Hsu, Hsien-Yi Cheng

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Abstract

The present disclosure provides a split gate MOSFET and a manufacturing method thereof. An epitaxy layer with a first conductivity type is formed on a substrate. A plurality of trenches are formed in the epitaxy layer. Impurities with a second conductive type is implanted and driven to the trenches to form a plurality of first doping areas. Since the first doping areas and none-doping areas of the epitaxy layer are alternately arranged with each other, and the first conductive type and the second conductive type are different conductivity types selected from P type or N type, the split gate MOSFET including the super junction structure is manufactured, and the advantages of simplifying manufacturing process, reducing cost and greatly reducing the on-resistance are achieved.

Claims12

Dependent claims

A manufacturing method of a split gate MOSFET, including steps of:

(a) providing a substrate, and forming an epitaxy layer with a first conductive type on the substrate;
(b) forming a mask oxide layer on the epitaxy layer;
(c) removing a part of the mask oxide layer and a part of the epitaxy layer to form a plurality of trenches;
(d) implanting first impurities with a second conductive type in a bottom and a sidewall of each of the trenches by an ion implanting process, and driving the first impurities to form a plurality of first doping areas in the epitaxy layer, wherein each of the first doping areas is diffused from the bottom and the sidewall of each of the trenches toward a direction away from the corresponding trenches, and a side of each of the first doping areas is diffused to in contact with the substrate, wherein the plurality of first doping areas and a plurality of none-doping areas of the epitaxy layer are alternatively arranged with each other, and the first conductive type and the second conductive type are different conductivity types selected from a P type or a N type;
(e) forming bottom oxide layers, a first gates and a second gates in each of the trenches, wherein the first gate and the second gate are separately formed in the corresponding bottom oxide layers;
(f) implanting second impurities on a second surface of the epitaxy layer by the ion implanting process, so as to form a plurality of second doping areas in the epitaxy layer, wherein each of the second doping areas is disposed between two neighboring trenches;
(g) implanting third impurities on the second surface of the epitaxy layer by the ion implanting process, so as to form a plurality of a plurality of third doping areas in the epitaxy layer, wherein each of the second doping areas is disposed between the corresponding third doping area and the corresponding none-doping area;
(h) forming a dielectric layer on the mask oxide layer and the second gate;
(i) removing a part of the dielectric layer, a part of the mask oxide layer and a part of the epitaxy layer to form a plurality of concaves;
(j) forming a plurality of contact areas in the plurality of concaves;
and
(k) forming a metal layer on the dielectric layer and the plurality of contact areas.

9 more elements

A split gate MOSFET, comprising:

a substrate;
an epitaxy layer formed on the substrate, having a first conductivity type and comprising a first surface, a second surface, a plurality of none-doping areas, a plurality of first doping areas, a plurality of second doping areas and a plurality of third doping areas, wherein the first surface and the second surface are two opposite surfaces of the epitaxy layer, and the first surface is in connection to the substrate, wherein the plurality of none-doping areas and the plurality of first doping areas are alternately arranged with each other;
a mask oxide layer formed on the epitaxy layer;
a plurality of split gate structures, each of the split gate structures comprises a trench, a bottom oxide layer, a first gate and a second gate, wherein the trench penetrates through the mask oxide layer, and is recessed from the second surface of the epitaxy layer toward the first surface, the bottom oxide layer is formed in the trench, the first gate and the second gate are formed in the bottom oxide layer and separated from each other, wherein each of the first doping areas is extended from a sidewall and a bottom of the corresponding one of the trenches toward the epitaxy layer and comprises first impurities with a second conductivity type, the first conductivity type and the second conductivity type are different conductivity types, wherein the plurality of third doping areas are disposed between two adjacent trenches, respectively, and in connection to the second surface, wherein the plurality of second doping areas are disposed between two adjacent trenches, respectively, and in connection to the corresponding one of the third doping areas
a dielectric layer formed on the mask oxide layer and the second gate, wherein a plurality of concaves are recessed from a top surface of the dielectric layer toward the epitaxy layer, each of the concaves penetrates the dielectric layer, the mask oxide layer and the third doping area, and at least a part of each of the concaves is formed in the second doping area;
a plurality of contact areas formed in the corresponding one of the plurality of concaves, respectively;
and
a metal layer formed on the dielectric layer and the plurality of contact areas.

5 more elements

Dependencies are inferred from the claim text.

Facts

Application: 18/422,306Filed 25 Jan 2024
Priority: TW 1121207572 Jun 2023
Published: 5 Dec 2024
Term ends: Not estimatedThe source records don’t support an estimate.

Classification14 codes

H10D 30/668
Vertical dmos [vdmos] fets: having trench gate electrodes, e.g. UMOS transistors
H10D 30/0295
Of vertical dmos [vdmos] fets: using recessing of the source electrodes
H10D 30/0297
Of vertical dmos [vdmos] fets: using recessing of the gate electrodes, e.g. to form trench gate electrodes
H10D 62/058
Forming charge compensation regions, e.g. superjunctions: by using trenches, e.g. implanting into sidewalls of trenches or refilling trenches

Family

No related US applications are recorded in the indexed filing history.

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