Field effect transistor and method of manufacturing thereof

A method of manufacturing a member, the method comprising:

• depositing a sacrificial layer on top of an epitaxial stack, the sacrificial layer indicating a location for a hole, the epitaxial stack comprising:
• a buffer layer comprising GaN,
• a barrier layer comprising Al—GaN arranged over the buffer layer, and
• a gate layer comprising p-doped GaN arranged over the barrier layer;
• etching the hole through the gate layer and the barrier layer as indicated by the sacrificial layer;
• regrowing a source layer comprising n-doped GaN in the hole;
• removing the sacrificial layer;
• structuring the gate layer to expose a portion of the barrier layer;
• depositing a passivation layer over the exposed portion of the barrier layer, the gate layer and the source layer;
• arranging one or more drain contacts on the barrier layer;
• arranging one or more gate contacts on the gate layer;
• and
• arranging a source contact on the source layer.

A field effect transistor (FET) comprising:

• a source contact;
• one or more gate contacts;
• one or more drain contacts,
• a junction FET (JFET) arranged to provide the source contact;
• and
• a first heterostructure FET and a second heterostructure FET, wherein the first and the second heterostructure FETs are arranged to provide the one or more gate contacts and the one or more drain contacts.