Methods of controlling breakdown voltage in microelectronic devices

A method, comprising:

• forming a transistor structure comprising:
• two source/drain (S/D) regions;
• a channel region horizontally interposed between the two S/D regions;
• two lightly doped drain (LDD) regions horizontally surrounding the two S/D regions, portions of the two LDD regions horizontally interposed between the channel region and the two S/D regions;
• a gate structure vertically overlying and horizontally overlapping the channel region;
• and
• gate dielectric material vertically interposed between and horizontally overlapping the gate structure and the channel region;
• and
• forming breakdown-enhanced implant (BEI) intrusions within the portions of the two LDD regions of the transistor, the BEI intrusions respectively having a different conductivity type than the LDD regions.

A method, comprising:

• forming circuity within P-type semiconductor structure, the circuity including N-doped metal-oxide-semiconductor (NMOS) structures respectively comprising:
• lightly doped drain (LDD) N− wells vertically extending into the P-type semiconductor structure;
• N+ source/drain (S/D) contact regions within the LDD N− wells;
• a channel region horizontally interposed between the LDD N− wells;
• and
• a gate electrode vertically overlying and horizontally overlapping the channel region;
• and
• forming P-type breakdown-enhanced implant (BEI) intrusions within the LDD N− wells of the NMOS structures, the P-type BEI intrusions individually horizontally interposed between the channel region and the N+ S/D contact regions of respective ones of the NMOS structures.