Panel-level semiconductor packaging method

A method of generating a die location check (DLC) file for determining true positions of a plurality of semiconductor devices for an electronic module in a reconstructed panel, comprising:

• conducting a post-bonding inspection for inspecting the plurality of semiconductor devices bonded on a marked carrier before forming the reconstructed panel;
• forming a molding layer for encapsulating the plurality of semiconductor devices mounted on the marked carrier for forming the reconstructed panel;
• and
• scanning the plurality of semiconductor devices in the reconstructed panel for detecting true positions of the semiconductor devices in the reconstructed panel.

A panel-level semiconductor packaging method for making a plurality of electronic modules, comprising:

• providing a marked carrier;
• aligning and bonding a plurality of semiconductor devices onto the marked carrier;
• forming a molding layer for forming a reconstructed panel;
• releasing the reconstructed panel from the marked carrier and then transferring the reconstructed panel to a carrier plate;
• forming a circuit layer on the plurality of semiconductor devices molded in the reconstructed panel by
• generating a die location check (DLC) file which comprises true positions of the plurality of semiconductor devices in the reconstructed panel;
• retrieving a green circuit file having green positions for the plurality of semiconductor devices;
• transforming the green circuit file to an adapted circuit file using the DLC file, wherein the green positions are aligned to the true positions for the plurality of semiconductor devices;
• and
• forming the circuit layer on the plurality of semiconductor devices at the true positions according to the adapted circuit file;
• forming an external connection layer on circuit layer;
• and
• singulating the reconstructed panel and the external connection layer into each of the plurality of electronic modules.