Semiconductor package

A semiconductor package, comprising:

• a first die having a signal region and a dummy region that surrounds the signal region in
• a plan view of the semiconductor package;
• and
• a second die stacked on the first die,
• wherein the first die includes:
• a plurality of first dummy patterns and a plurality of second dummy patterns that extend in a first direction on the dummy region and are alternately arranged in a second direction that intersects the first direction;
• a first dielectric layer on the first dummy patterns and the second dummy patterns;
• a plurality of first pads on the first dummy patterns;
• and
• a plurality of second pads on the second dummy patterns,
• wherein the second die includes:
• a plurality of third pads on the dummy region at positions that correspond to positions of the first pads;
• and
• a plurality of fourth pads at positions that correspond to positions of the second pads,
• wherein the third pads are electrically connected through the first pads to the first dummy patterns, and
• wherein the fourth pads are electrically insulated from the second dummy patterns.

A semiconductor package, comprising:

• a substrate;
• a first die on the substrate and having a signal region and a dummy region that surrounds the signal region in a plan view of the semiconductor package;
• a second die stacked on the first die;
• and
• a molding layer on the substrate and surrounding the first die and the second die in the plan view of the semiconductor package,
• wherein the first die includes:
• a plurality of first dummy patterns and a plurality of second dummy patterns that are alternately arranged in a first direction on the dummy region;
• a first dielectric layer on the first dummy patterns and the second dummy patterns;
• a plurality of first pads that are arranged to constitute at least one row that extends along a second direction on the first dummy patterns, the second direction intersecting the first direction;
• and
• a plurality of second pads that are arranged to constitute one row that extends along the second direction on the second dummy patterns,
• wherein the second die includes:
• a plurality of third pads on the dummy region at positions that correspond to positions of the first pads;
• and
• a plurality of fourth pads at positions that correspond to positions of the second pads,
• wherein the first pads are in contact with the second pads and the first dummy patterns,
• wherein the first dielectric layer is between the fourth pads and the second pads or between the second pads and the second dummy patterns, and
• wherein the first dummy patterns are connected to a ground circuit or a power circuit of the first die.