Wiring substrate, array substrate and light emitting module having control regions arranged into control region rows and control region columns

A light emitting module, comprising an array substrate, the array substrate comprising a wiring substrate,

• the wiring substrate comprises a plurality of control regions distributed in an array, wherein the plurality of control regions are arranged into a plurality of control region rows and a plurality of control region columns;
• each of the control region columns comprises at least two of the control regions arranged along a first direction;
• each of the control region rows comprises at least two of the control regions arranged along a second direction;
• and the second direction is parallel to a plane where the wiring substrate is located and intersects with the first direction;
• each of the control regions comprises four device regions distributed in an array;
• the device regions are configured to set up functional devices that are electrically connected to each other;
• and the four device regions in each of the control regions are respectively a first device region, a second device region, a third device region, and a fourth device region;
• wherein the first device region is the device region located in the first row along the first direction and in the first column along the second direction in the control region, the second device region is the device region located in the first row along the first direction and in the second column along the second direction in the control region, the third device region is the device region located in the second row along the first direction and in the first column along the second direction in the control region, and the fourth device region is the device region located in the second row along the first direction and in the second column along the second direction in the control region;
• the wiring substrate comprises a base substrate, a first metal wiring layer, and an insulating material layer that are stacked in sequence, wherein the first metal wiring layer is provided with drive leads extending along the first direction;
• in each of the control region columns, the drive leads comprise at least a first power voltage lead, a first input lead, a reference voltage lead, a second input lead, and a second power voltage lead that are sequentially arranged along the second direction;
• the wiring substrate further comprises at least one signal channel extending along the first direction, each of the signal channels comprising at least one of the control region columns;
• and in each of the signal channels, the drive leads further comprise at least one address lead;
• the control regions comprise first control regions, wherein in one of the first control regions, the insulating material layer is provided with a first, second, third, fourth, fifth and sixth power via hole, a first, second, third and fourth input via hole, and a first and second reference via hole;
• the first, second and third power via holes are arranged in sequence along the first direction and respectively expose a partial region of the first power voltage lead;
• the first power via hole is located at a side of the device region A (1,1) away from the device region A (2,1) or located between the device region A (1,1) and the device region A (2,1);
• the second power via hole is located between the device region A (1, 1) and the device region A (2, 1);
• and the third power via hole is located at a side of the device region A (2, 1) away from the device region A (1,1);
• the fourth, fifth and sixth power via holes are arranged in sequence along the first direction and respectively expose a partial region of the second power voltage lead;
• the fourth power via hole is located at a side of the second device region away from the fourth device region or located between the second device region and the fourth device region;
• the fifth power via hole is located between the second device region and the fourth device region;
• and the sixth power via hole is located at a side of the fourth device region away from the second device region;
• the first input via hole and the second input via hole respectively expose a partial region of the first input lead;
• the first input via hole is located between an edge of the first device region away from the third device region and an edge of the third device region close to the first device region;
• and the second input via hole is located at a side of the third device region away from the first device region;
• the third input via hole and the fourth input via hole respectively expose a partial region of the second input lead;
• the third input via hole is located between an edge of the second device region away from the fourth device region and an edge of the fourth device region close to the second device region;
• and the fourth input via hole is located at a side of the fourth device region away from the second device region;
• the first reference via hole and the second reference via hole respectively expose a partial region of the reference voltage lead;
• and along the first direction, the first reference via hole is located between the first device region and the third device region, and the second reference via hole is located at a side of the third device region away from the first device region;
• and
• in each of the signal channels, the insulating material layer is further provided with at least one address via hole that exposes a partial region of the at least one address lead,
• wherein
• the array substrate further comprises:
• a second metal wiring layer and an insulating protection layer which are sequentially laminated on a side of the insulating material layer of the wiring substrate away from the base substrate;
• and
• multiple functional devices and multiple microchips, wherein
• the second metal wiring layer comprises a plurality of connection leads, a plurality of device pad groups and a plurality of chip pad groups, wherein the functional devices are bound and connected to the device pad groups, the microchips are connected to the chip pad groups, the device pad groups and the chip pad groups are connected to the connection leads, and at least part of the connection leads is connected to the first metal wiring layer through at least part of the via holes provided on the insulating material layer,
• wherein
• a device control circuit is provided in each of the device regions, and the device control circuit comprises one of the functional devices or a plurality of the functional devices electrically connected to one another;
• in the first control region, a connection between a first end of the device control circuit in the first device region and the first power voltage lead is made through the connection lead that overlaps with the first power via hole;
• a connection between a first end of the device control circuit in the third device region and the first power voltage lead is made through the connection lead that overlaps with the second power via hole or the third power via hole;
• a connection between a first end of the device control circuit in the second device region and the second power voltage lead is made through the connection lead that overlaps with the fourth power via hole;
• and a connection between a first end of the device control circuit in the fourth device region and the second power voltage lead is made through the connection lead that overlaps with the fifth power via hole or the sixth power via hole,
• wherein
• in one of the control regions, the array substrate is provided with four chip pad groups each corresponding to a respective one of the four device regions;
• each of the chip pad groups comprises a reference voltage sub-pad, an output sub-pad, a first input sub-pad and a second input sub-pad;
• and a second end of the device control circuit in each of the device region is connected to the output sub-pad of the chip pad group corresponding to the device region through the connection lead;
• in one of the signal channels, each of the device regions is sequentially numbered, and the device region with a serial number of 1 is located at an end along the first direction of the signal channel;
• the chip pad groups each corresponding to a respective one of the device regions are sequentially cascaded according to the serial number of the device regions;
• a connection between the second input sub-pad of the chip pad group corresponding to the device region with a serial number of 1 and one of the address leads is made through the connection lead that overlaps with the address via hole;
• and the output sub-pad of the chip pad group corresponding to the device region with a serial number of (n−1) is connected with the second input sub-pad of the chip pad group corresponding to the device region with a serial number of n by the connection lead, n being a positive integer greater than 1 and not greater than the number of the device regions in one signal channel;
• in each of the first control regions, the reference voltage sub-pad of the chip pad group corresponding to the first device region and the reference voltage sub-pad of the chip pad group corresponding to the second device region are connected with the reference voltage lead through the connection lead that overlaps with the first reference via hole;
• the reference voltage sub-pad of the chip pad group corresponding to the third device region and the reference voltage sub-pad of the chip pad group corresponding to the fourth device region are connected with the reference voltage lead through the connection lead that overlaps with the second reference via hole;
• the first input sub-pad of the chip pad group corresponding to the first device region and the first input lead are connected through the connection lead that overlaps with the first input via hole;
• the first input sub-pad of the chip pad group corresponding to the third device region and the first input lead are connected through the connection lead that overlaps with the second input via hole;
• the first input sub-pad of the chip pad group corresponding to the second device region and the second input lead are connected through the connection lead that overlaps with the third input via hole;
• and a connection between the first input sub-pad of the chip pad group corresponding to the fourth device region and the second input lead is made through the connection lead that overlaps with the fourth input via hole.