Semiconductor devices for detecting defects in error correction circuits, and methods of performing test mode operations

Abstract

A semiconductor device includes a read circuit configured to latch read parity including error information on read data output from a memory circuit to generate latch parity when a test read control signal is enabled. The semiconductor device also includes a parity selection circuit configured to output the latch parity as parity when a test selection signal is enabled. The semiconductor device further includes a write circuit configured to receive write data generated from data and the parity, and to correct error of the write data, based on write parity including error information on the write data and the parity to generate correction data when a test write control signal is enabled.

Dependencies are inferred from the claim text.