Fly shared bit line on 4-cpp static random access memory (sram) cell and array

A semiconductor device, comprising:

• a first memory array including a plurality of first memory cells that are formed over a first portion of a substrate;
• a second memory array including a plurality of second memory cells that are formed over a second portion of the substrate, wherein the second portion is physically separated from the first portion along a first lateral direction;
• a first pair of bit lines physically extend across the first portion and terminates at the second portion;
• and
• a second pair of bit lines physically extend across both of the first portion and the second portion.

A method for making memory arrays, comprising:

• arranging first and second memory cells over a first portion of a substrate and third and fourth memory cells over a second portion of the substrate, the first portion being separated from the second portion along a first lateral direction, wherein each of the first to four memory cells comprises a plurality of transistors formed based on a four contacted polysilicon pitch (4CPP) architecture;
• connecting a first word line and a second word line to the first memory cell and the second memory cell, respectively;
• connecting a third word line and a fourth word line to the third memory cell and the fourth memory cell, respectively;
• connecting a first pair of bit lines to the first and second memory cells;
• and
• connecting a second pair of bit lines to the third and fourth memory cells;
• wherein the first pair of bit lines, along the first lateral direction, physically extend across the first portion and terminates at the second portion, and the second pair of bit lines, along the first lateral direction, physically extend across both of the first portion and the second portion.