US 2024/0404582 A1 · MEMORY CONTROLLER SUPPORT FOR MIXED READ

Abstract

Technology is disclosed for controlling reads in a memory device supporting different types of reads having different performance times (e.g., a relatively fast read such as a globally-referenced read and a slower read such as a self-referenced read). The data out latencies of the different read types may be different to accommodate the different performance times. The memory controller may mix the different types of reads. The memory controller tracks expected usage of the data bus and schedules read commands accordingly to avoid data collisions. A countdown timer may be used to track the earliest clock cycle at which the memory device may return data for a new read command to be issued. The memory controller may record what clock cycles the data bus is projected to be occupied with data and schedule read commands based on the projected data bus occupancy to avoid data collisions.

Claims20

Dependent claims

An apparatus comprising:

a communication interface configured to connect to read circuitry that is configured to read memory cells, the read circuitry configured to perform a first type of read having a first performance time and a second type of read having a second performance time that is longer than the first performance time;
and
one or more control circuits coupled to the communication interface, the one or more control circuits configured to:
track expected usage of the communication interface to return data by the read circuitry in response to read commands of the first type and the second type, wherein the first type of read command has a first data out latency and the second type of read command has a second data out latency that is longer than the first data out latency;
and
control timing of issuance of read commands of the first type and the second type to meet a timing constraint for data returned from the read circuitry on the communication interface.

3 more elements

A method for reading memory, the method comprising:

determining, by a memory controller, first times to issue commands for a first type of read command having a first data out latency that will not result in a collision on a data interface;
issuing commands for the first type of read command from the memory controller over a command interface to a memory device at the first times;
determining, by the memory controller, second times to issue commands for a second type of read command having a second data out latency that will not result a collision on the data interface, wherein the second data out latency is greater than the first data out latency;
and
issuing commands for the second type of read command from the memory controller over the command interface to the memory device at the second times.

2 more elements

A memory system, comprising:

a plurality of memory cells;
a first control circuit communicatively coupled to the plurality of memory cells, the first control circuit configured to perform a globally-referenced read of the memory cells and a self-referenced read of the memory cells;
a data interface communicatively coupled to the first control circuit;
a command interface communicatively coupled to the first control circuit;
and
a second control circuit communicatively coupled to the data interface and the command interface, wherein the second control circuit is configured to:
determine first times at which first commands of a first type of read having a first data out latency and second times at which second commands of a second type of read having a second data out latency can be issued on the command interface while avoiding data collisions on the data interface, wherein the second data out latency is longer than the first data out latency;
issue the first commands at the first times on the command interface to instruct the first control circuit to perform the globally-referenced read;
and
issue the second commands at the second times on the command interface to instruct the first control circuit to perform the self-referenced read.

7 more elements

Dependencies are inferred from the claim text.

Memory controller support for mixed read

Life of this patent

Memory controller support for mixed read

Life of this patent

Abstract

Claims20